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rev.3.2 S1D15705 series technical manual
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind aris ing out of any inaccuracies c ontained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyri ght infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. all other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ?seiko epson corporation 2005, all rights reserved.
configuration of product number devices s1 d 15705 d 00b0 00 packing specification specifications shape (d:chip, t:tcp, f:qfp) model number model name (d:lcd driver) product classification (s1:semiconductors)
?i contents 1. description .................................................................................................................. ................................. 1 2. features ..................................................................................................................... .................................... 1 3. block diagram ................................................................................................................ .............................. 3 4. pad .......................................................................................................................... .......................................... 4 5. pin description .............................................................................................................. ............................ 14 6. function description ......................................................................................................... ..................... 18 7. command ...................................................................................................................... ................................. 38 8. command setting .............................................................................................................. ........................ 50 9. absolute maximum ratings ..................................................................................................... .............. 54 10. dc characteristics .......................................................................................................... ........................ 55 11. microprocessor (mpu) interface: reference .............................................................................. 70 12. connection between lcd drivers: reference ............................................................................. 71 13. lcd panel wiring: reference ................................................................................................. .............. 72 14. tcp pin layout .............................................................................................................. .............................. 73 15. tcp dimensions .............................................................................................................. ............................. 74 16. temperature sensor circuit .................................................................................................. ............. 75 17. cautions .................................................................................................................... ................................... 78 rev. 3.2
S1D15705 series technical manual rev. 3.2 epson 1 1. description the S1D15705 series is a 1-chip dot matrix liquid crystal driver that can be connected to the bus of a microcomputer. it stores the 8-bit parallel or serial display data sent from the microcomputer in the built-in display data ram and generates liquid crystal drive signals independently of the microcomputer. since it incorporates 65 200 bits of the display data ram and the one-dot pixel of the liquid crystal panel and one bit of the built-in ram have a one-to-one correspondence, it enables display with the high degree of freedom. the S1D15705 series incorporates 65 circuits of the common output and 168 circuits of the segment output and can display 65 168 dots (capable of displaying 10 columns 4 rows of a 16 16 dot kanji font) using the single chip. the s1d15707 series incorporates 33 circuits of the common output and 200 circuits of the segment output and can display 33 200 dots (capable of displaying 12 columns 2 rows of a 16 16 dot kanji font). the s1d15708 series incorporates 17 circuits of the common output and 200 circuits of the segment output and can display 17 200 dots (capable of displaying 12 columns 1 rows of a 16 16 dot kanji font). it can also expand the display capacity by using the two chips for the master and slave configuration. incorporating an analog temperature sensor circuit, the S1D15705 * 10 ** can be used to constitute a system to provide optimum lcd contrast throughout a wide temperature range without need for use of supplementary parts such as the thermistor, under controls of a microcomputer. since the read/write operation of the display data ram does not require external operation clocks, the S1D15705 series can be operated with the minimum current consumption. since it also incorporates a liquid crystal drive power supply with low current consumption, liquid crystal drive power supply voltage adjusting resistor, and display clock cr oscillator circuit, it can provide a display system for high performance handy equipment with the minimum current consumption and the minimum parts configuration. 2. features direct display of ram data using the display data ram ram bit data ??.... goes on. ??.... goes off (at display normal rotation). ram capacity 65 200 = 13,000 bits liquid crystal drive circuit the S1D15705 series 65 circuits for the common output and 168 circuits for the segment output the s1d15707 series 33 circuits for the common output and 200 circuits for the segment output the s1d15708 series 17 circuits for the common output and 200 circuits for the segment output high-speed 8-bit mpu interface (both the 80 and 68 series mups can directly be connected.)/serial interface enabled abundant command functions display data read/write, display on/off, display normal rotation/reversal, page address set, display start line set, column address set, status read, power supply save display all lighting on/off, lcd bias set, read modify write, segment driver direction select, electronic control, v 5 voltage adjusting built-in resistance ratio set, static indicator, n line alternating current reversal drive, common output state selection, and built-in oscillator circuit on built-in static drive circuit for indicators (one set, blinking speed variable) built-in power supply circuit for low power supply liquid crystal drive booster circuit (boosting magnification - double, triple, quadruple, boosting reference power supply external input enabled) 3% high accuracy alternating current voltage adjusting circuit (temperature gradient: ?.05%/ c) built-in v 5 voltage adjusting resistor, built-in v 1 to v4 voltage generation split resistors, built-in electronic control function, and voltage follower built-in cr oscillator circuit (external clock input enabled) ultra-low power consumption built-in temperature sensor circuit (S1D15705d10b * ) power supplies logic power supply: v dd ?v ss = 2.4 to 3.6 v (S1D15705 * 03 ** , s1d15707 * 03 ** ) v dd ?v ss = 3.6 to 5.5 v (S1D15705 * 00 ** , s1d15707 * 00 ** , s1d15708 * 00 ** ) boosting reference power supply: v dd ?v ss = 1.8 to 6.0 v liquid crystal drive power supply: v 5 ?v dd = ?.5 to ?8.0 v (S1D15705 ***** ) /?.5 v to ?6.0 v (s1d15707 ***** ) /?.5 v to ?0.0 (s1d15708 ***** ) wide operating temperature range ?0 to 85 c cmos process shipping form bare chip, tcp no light-resistant and radiation-resistant design are provided.
S1D15705 series technical manual 2 epson rev. 3.2 series specification product voltage duty bias seg dr com dr v reg temperature shipping name [v] gradient form S1D15705d00b * C3.6 to C5.5 1/65 1/9, 1/7 168 65 C0.05%/ c bare chip S1D15705d10b * C3.6 to C5.5 1/65 1/9, 1/7 168 65 C0.05%/ c bare chip S1D15705d03b * C2.4 to C3.6 1/65 1/9, 1/7 168 65 C0.05%/ c bare chip S1D15705t00a * C3.6 to C5.5 1/65 1/9, 1/7 168 65 C0.05%/ c tcp S1D15705t03a * C2.4 to C3.6 1/65 1/9, 1/7 168 65 C0.05%/ c tcp s1d15707d00b * C3.6 to C5.5 1/33 1/6, 1/5 200 33 C0.05%/ c bare chip s1d15707d03b * C2.4 to C3.6 1/33 1/6, 1/5 200 33 C0.05%/ c bare chip s1d15707t00 ** C3.6 to C5.5 1/33 1/6, 1/5 200 33 C0.05%/ c tcp s1d15707t03 ** C2.4 to C3.6 1/33 1/6, 1/5 200 33 C0.05%/ c tcp s1d15708d00b * C3.6 to C5.5 1/17 1/6, 1/5 200 17 C0.05%/ c bare chip ? specifications for circuits other than the temperature sensor circuit are the same as those of the S1D15705d00b * .
S1D15705 series technical manual rev. 3.2 epson 3 3. block diagram example : S1D15705 ***** v ss v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 v r v rs irs hpm cap1+ cap1 C cap2 C cap2+ cap3 C frs cls oscillator circuit display timing generator circuit line address i/o buffer fr cl sync dof m/s cs1 cs2 a0 rd (e) wr (r/w) p/s res d7 (si) d6 (scl) d5 d4 d3 d2 d1 d0 seg0 seg167 com0 com63 coms ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? coms com drivers seg drivers display data latch circuit display data ram 200 x 65 column address status command decoder mpu interface bus holder shift register power supply circuit page address
S1D15705 series technical manual 4 epson rev. 3.2 item size unit xy chip size 13.30 4. pad pad layout S1D15705 series (0, 0) 94 93 1 129 302 128 337 303 die no. (ex. S1D15705d00b * ) d1575d 0b
S1D15705 series technical manual rev. 3.2 epson 5 pad pin xy no. name 1 (nc) 6195 1246 2 (nc) 6059 3 sync 5922 4 frs 5786 5 fr 5649 6 cl 5513 7 dof 5376 8 sync 5240 9v ss 5103 10 cs1 4967 11 cs2 4830 12 v dd 4694 13 res 4557 14 a0 4421 15 v ss 4284 16 wr, r/w 4148 17 rd, e 4011 18 v dd 3875 19 d0 3738 20 d1 3602 21 d2 3465 22 d3 3329 23 d4 3192 24 d5 3056 25 d6 (scl) 2919 26 d7 (si) 2783 27 v dd 2646 28 v dd 2512 29 v dd 2378 30 v dd 2245 31 v dd 2111 32 v ss 1977 33 v ss 1843 34 v ss 1709 35 v ss2 1575 36 v ss2 1441 37 v ss2 1307 38 v ss2 1173 39 v ss2 1039 40 (nc) 906 41 v out 772 42 v out 638 43 cap3 C 504 44 cap3 C 370 45 (nc) 236 46 cap1+ 102 47 cap1+ C 32 48 cap1 CC 166 49 cap1 CC 300 50 cap2 CC 433 pad pin xy no. name 51 cap2 CC 567 1246 52 cap2+ C 701 53 cap2+ C 835 54 v ss C 969 55 v ss C 1103 56 v rs C 1237 57 v rs C 1371 58 v dd C 1505 59 v dd C 1639 60 v 1 C 1772 61 v 1 C 1906 62 v 2 C 2040 63 v 2 C 2174 64 (nc) C 2308 65 v 3 C 2442 66 v 3 C 2576 67 v 4 C 2710 68 v 4 C 2844 69 v 5 C 2978 70 v 5 C 3111 71 (nc) C 3245 72 v r C 3379 73 test1 C 3513 74 test2 C 3647 75 test3 C 3781 76 test4 C 3915 77 v dd C 4049 78 m/s C 4185 79 cls C 4322 80 v ss C 4458 81 c86 C 4595 82 p/s C 4731 83 v dd C 4868 84 hpm C 5004 85 v ss C 5141 86 irs C 5277 87 v dd C 5414 88 test5 C 5550 89 test6 C 5687 90 test7 C 5836 91 test8 C 5956 92 test9 C 6076 93 (nc) C 6195 94 (nc) C 6474 1248 95 com31 1163 96 com30 1090 97 com29 1017 98 com28 945 99 com27 872 100 com26 799 pad pin xy no. name 101 com25 C 6474 727 102 com24 654 103 com23 581 104 com22 509 105 com21 436 106 com20 363 107 com19 291 108 com18 218 109 com17 145 110 com16 73 111 com15 0 112 com14 C 73 113 com13 C 145 114 com12 C 218 115 com11 C 291 116 com10 C 363 117 com9 C 436 118 com8 C 509 119 com7 C 581 120 com6 C 654 121 com5 C 727 122 com4 C 800 123 com3 C 872 124 com2 C 945 125 com1 C 1018 126 com0 C 1090 127 coms C 1163 128 (nc) C 1248 129 (nc) C 6232 C 1246 130 (nc) C 6147 131 (nc) C 6075 132 seg0 C 6002 133 seg1 C 5930 134 seg2 C 5859 135 seg3 C 5787 136 seg4 C 5715 137 seg5 C 5643 138 seg6 C 5571 139 seg7 C 5499 140 seg8 C 5427 141 seg9 C 5355 142 seg10 C 5283 143 seg11 C 5212 144 seg12 C 5140 145 seg13 C 5068 146 seg14 C 4996 147 seg15 C 4924 148 seg16 C 4852 149 seg17 C 4780 150 seg18 C 4708 S1D15705 ***** pad central coordinates unit: m
S1D15705 series technical manual 6 epson rev. 3.2 pad pin xy no. name 201 seg69 C 1042 C 1246 202 seg70 C 970 203 seg71 C 898 204 seg72 C 826 205 seg73 C 754 206 seg74 C 682 207 seg75 C 611 208 seg76 C 539 209 seg77 C 467 210 seg78 C 395 211 seg79 C 323 212 seg80 C 251 213 seg81 C 179 214 seg82 C 107 215 seg83 C 35 216 seg84 36 217 seg85 108 218 seg86 180 219 seg87 252 220 seg88 324 221 seg89 396 222 seg90 468 223 seg91 540 224 seg92 612 225 seg93 683 226 seg94 755 227 seg95 827 228 seg96 899 229 seg97 971 230 seg98 1043 231 seg99 1115 232 seg100 1187 233 seg101 1259 234 seg102 1330 235 seg103 1402 236 seg104 1474 237 seg105 1546 238 seg106 1618 239 seg107 1690 240 seg108 1762 241 seg109 1834 242 seg110 1906 243 seg111 1977 244 seg112 2049 245 seg113 2121 246 seg114 2193 247 seg115 2265 248 seg116 2337 249 seg117 2409 250 seg118 2481 pad pin xy no. name 251 seg119 2553 C 1246 252 seg120 2625 253 seg121 2696 254 seg122 2768 255 seg123 2840 256 seg124 2912 257 seg125 2984 258 seg126 3056 259 seg127 3128 260 seg128 3200 261 seg129 3272 262 seg130 3343 263 seg131 3415 264 seg132 3487 265 seg133 3559 266 seg134 3631 267 seg135 3703 268 seg136 3775 269 seg137 3847 270 seg138 3919 271 seg139 3990 272 seg140 4062 273 seg141 4134 274 seg142 4206 275 seg143 4278 276 seg144 4350 277 seg145 4422 278 seg146 4494 279 seg147 4566 280 seg148 4637 281 seg149 4709 282 seg150 4781 283 seg151 4853 284 seg152 4925 285 seg153 4997 286 seg154 5069 287 seg155 5141 288 seg156 5213 289 seg157 5284 290 seg158 5356 291 seg159 5428 292 seg160 5500 293 seg161 5572 294 seg162 5644 295 seg163 5716 296 seg164 5788 297 seg165 5860 298 seg166 5931 299 seg167 6003 300 (nc) 6075 pad pin xy no. name 151 seg19 C 4636 C 1246 152 seg20 C 4564 153 seg21 C 4493 154 seg22 C 4421 155 seg23 C 4349 156 seg24 C 4277 157 seg25 C 4205 158 seg26 C 4133 159 seg27 C 4061 160 seg28 C 3989 161 seg29 C 3917 162 seg30 C 3846 163 seg31 C 3774 164 seg32 C 3702 165 seg33 C 3630 166 seg34 C 3558 167 seg35 C 3486 168 seg36 C 3414 169 seg37 C 3342 170 seg38 C 3270 171 seg39 C 3199 172 seg40 C 3127 173 seg41 C 3055 174 seg42 C 2983 175 seg43 C 2911 176 seg44 C 2839 177 seg45 C 2767 178 seg46 C 2695 179 seg47 C 2623 180 seg48 C 2552 181 seg49 C 2480 182 seg50 C 2408 183 seg51 C 2336 184 seg52 C 2264 185 seg53 C 2192 186 seg54 C 2120 187 seg55 C 2048 188 seg56 C 1976 189 seg57 C 1905 190 seg58 C 1833 191 seg59 C 1761 192 seg60 C 1689 193 seg61 C 1617 194 seg62 C 1545 195 seg63 C 1473 196 seg64 C 1401 197 seg65 C 1329 198 seg66 C 1258 199 seg67 C 1186 200 seg68 C 1114 unit: m
S1D15705 series technical manual rev. 3.2 epson 7 unit: m pad pin xy no. name 301 (nc) 6147 C 1246 302 (nc) 6232 C 1248 304 com32 C 1163 305 com33 C 1090 306 com34 C 1018 307 com35 C 945 308 com36 C 872 309 com37 C 800 310 com38 C 727 311 com39 C 654 312 com40 C 581 313 com41 C 509 314 com42 C 436 315 com43 C 363 316 com44 C 291 317 com45 C 218 318 com46 C 145 319 com47 C 73 320 com48 0 321 com49 73 322 com50 145 323 com51 218 324 com52 291 325 com53 363 326 com54 436 327 com55 509 328 com56 581 329 com57 654 330 com58 727 331 com59 799 332 com60 872 333 com61 945 334 com62 1017 335 com63 1090 336 coms 1163 337 (nc) 1248
S1D15705 series technical manual 8 epson rev. 3.2 pad pin xy no. name 1 (nc) 6195 1246 2 (nc) 6059 3 sync 5922 4 frs 5786 5 fr 5649 6 cl 5513 7 dof 5376 8 sync 5240 9v ss 5103 10 cs1 4967 11 cs2 4830 12 v dd 4694 13 res 4557 14 a0 4421 15 v ss 4284 16 wr, r/w 4148 17 rd, e 4011 18 v dd 3875 19 d0 3738 20 d1 3602 21 d2 3465 22 d3 3329 23 d4 3192 24 d5 3056 25 d6 (scl) 2919 26 d7 (si) 2783 27 v dd 2646 28 v dd 2512 29 v dd 2378 30 v dd 2245 31 v dd 2111 32 v ss 1977 33 v ss 1843 34 v ss 1709 35 v ss2 1575 36 v ss2 1441 37 v ss2 1307 38 v ss2 1173 39 v ss2 1039 40 (nc) 906 41 v out 772 42 v out 638 43 cap3 C 504 44 cap3 C 370 45 (nc) 236 46 cap1+ 102 47 cap1+ C 32 48 cap1 CC 166 49 cap1 CC 300 50 cap2 CC 433 pad pin xy no. name 51 cap2 CC 567 1246 52 cap2+ C 701 53 cap2+ C 835 54 v ss C 969 55 v ss C 1103 56 v rs C 1237 57 v rs C 1371 58 v dd C 1505 59 v dd C 1639 60 v 1 C 1772 61 v 1 C 1906 62 v 2 C 2040 63 v 2 C 2174 64 (nc) C 2308 65 v 3 C 2442 66 v 3 C 2576 67 v 4 C 2710 68 v 4 C 2844 69 v 5 C 2978 70 v 5 C 3111 71 (nc) C 3245 72 v r C 3379 73 test1 C 3513 74 test2 C 3647 75 test3 C 3781 76 test4 C 3915 77 v dd C 4049 78 m/s C 4185 79 cls C 4322 80 v ss C 4458 81 c86 C 4595 82 p/s C 4731 83 v dd C 4868 84 hpm C 5004 85 v ss C 5141 86 irs C 5277 87 v dd C 5414 88 test5 C 5550 89 test6 C 5687 90 test7 C 5836 91 test8 C 5956 92 test9 C 6076 93 (nc) C 6195 94 (nc) C 6474 1248 95 com31 1163 96 com30 1090 97 com29 1017 98 com28 945 99 com27 872 100 com26 799 pad pin xy no. name 101 com25 C 6474 727 102 com24 654 103 com23 581 104 com22 509 105 com21 436 106 com20 363 107 com19 291 108 com18 218 109 com17 145 110 com16 73 111 com15 0 112 com14 C 73 113 com13 C 145 114 com12 C 218 115 com11 C 291 116 com10 C 363 117 com9 C 436 118 com8 C 509 119 com7 C 581 120 com6 C 654 121 com5 C 727 122 com4 C 800 123 com3 C 872 124 com2 C 945 125 com1 C 1018 126 com0 C 1090 127 coms C 1163 128 (nc) C 1248 129 (nc) C 6232 C 1246 130 (nc) C 6147 131 (nc) C 6075 132 seg0 C 6002 133 seg1 C 5930 134 seg2 C 5859 135 seg3 C 5787 136 seg4 C 5715 137 seg5 C 5643 138 seg6 C 5571 139 seg7 C 5499 140 seg8 C 5427 141 seg9 C 5355 142 seg10 C 5283 143 seg11 C 5212 144 seg12 C 5140 145 seg13 C 5068 146 seg14 C 4996 147 seg15 C 4924 148 seg16 C 4852 149 seg17 C 4780 150 seg18 C 4708 s1d15707 ***** pad central coordinates unit: m
S1D15705 series technical manual rev. 3.2 epson 9 unit: m pad pin xy no. name 151 seg19 C 4636 C 1246 152 seg20 C 4564 153 seg21 C 4493 154 seg22 C 4421 155 seg23 C 4349 156 seg24 C 4277 157 seg25 C 4205 158 seg26 C 4133 159 seg27 C 4061 160 seg28 C 3989 161 seg29 C 3917 162 seg30 C 3846 163 seg31 C 3774 164 seg32 C 3702 165 seg33 C 3630 166 seg34 C 3558 167 seg35 C 3486 168 seg36 C 3414 169 seg37 C 3342 170 seg38 C 3270 171 seg39 C 3199 172 seg40 C 3127 173 seg41 C 3055 174 seg42 C 2983 175 seg43 C 2911 176 seg44 C 2839 177 seg45 C 2767 178 seg46 C 2695 179 seg47 C 2623 180 seg48 C 2552 181 seg49 C 2480 182 seg50 C 2408 183 seg51 C 2336 184 seg52 C 2264 185 seg53 C 2192 186 seg54 C 2120 187 seg55 C 2048 188 seg56 C 1976 189 seg57 C 1905 190 seg58 C 1833 191 seg59 C 1761 192 seg60 C 1689 193 seg61 C 1617 194 seg62 C 1545 195 seg63 C 1473 196 seg64 C 1401 197 seg65 C 1329 198 seg66 C 1258 199 seg67 C 1186 200 seg68 C 1114 pad pin xy no. name 201 seg69 C 1042 C 1246 202 seg70 C 970 203 seg71 C 898 204 seg72 C 826 205 seg73 C 754 206 seg74 C 682 207 seg75 C 611 208 seg76 C 539 209 seg77 C 467 210 seg78 C 395 211 seg79 C 323 212 seg80 C 251 213 seg81 C 179 214 seg82 C 107 215 seg83 C 35 216 seg84 36 217 seg85 108 218 seg86 180 219 seg87 252 220 seg88 324 221 seg89 396 222 seg90 468 223 seg91 540 224 seg92 612 225 seg93 683 226 seg94 755 227 seg95 827 228 seg96 899 229 seg97 971 230 seg98 1043 231 seg99 1115 232 seg100 1187 233 seg101 1259 234 seg102 1330 235 seg103 1402 236 seg104 1474 237 seg105 1546 238 seg106 1618 239 seg107 1690 240 seg108 1762 241 seg109 1834 242 seg110 1906 243 seg111 1977 244 seg112 2049 245 seg113 2121 246 seg114 2193 247 seg115 2265 248 seg116 2337 249 seg117 2409 250 seg118 2481 pad pin xy no. name 251 seg119 2553 C 1246 252 seg120 2625 253 seg121 2696 254 seg122 2768 255 seg123 2840 256 seg124 2912 257 seg125 2984 258 seg126 3056 259 seg127 3128 260 seg128 3200 261 seg129 3272 262 seg130 3343 263 seg131 3415 264 seg132 3487 265 seg133 3559 266 seg134 3631 267 seg135 3703 268 seg136 3775 269 seg137 3847 270 seg138 3919 271 seg139 3990 272 seg140 4062 273 seg141 4134 274 seg142 4206 275 seg143 4278 276 seg144 4350 277 seg145 4422 278 seg146 4494 279 seg147 4566 280 seg148 4637 281 seg149 4709 282 seg150 4781 283 seg151 4853 284 seg152 4925 285 seg153 4997 286 seg154 5069 287 seg155 5141 288 seg156 5213 289 seg157 5284 290 seg158 5356 291 seg159 5428 292 seg160 5500 293 seg161 5572 294 seg162 5644 295 seg163 5716 296 seg164 5788 297 seg165 5860 298 seg166 5931 299 seg167 6003 300 (nc) 6075
S1D15705 series technical manual 10 epson rev. 3.2 unit: m pad pin xy no. name 301 (nc) 6147 C 1246 302 (nc) 6232 C 1248 304 seg168 C 1163 305 seg169 C 1090 306 seg170 C 1018 307 seg171 C 945 308 seg172 C 872 309 seg173 C 800 310 seg174 C 727 311 seg175 C 654 312 seg176 C 581 313 seg177 C 509 314 seg178 C 436 315 seg179 C 363 316 seg180 C 291 317 seg181 C 218 318 seg182 C 145 319 seg183 C 73 320 seg184 0 321 seg185 73 322 seg186 145 323 seg187 218 324 seg188 291 325 seg189 363 326 seg190 436 327 seg191 509 328 seg192 581 329 seg193 654 330 seg194 727 331 seg195 799 332 seg196 872 333 seg197 945 334 seg198 1017 335 seg199 1090 336 coms 1163 337 (nc) 1248
S1D15705 series technical manual rev. 3.2 epson 11 s1d15708 ***** pad central coordinates unit: m pad pin xy no. name 1 (nc) 6159 1246 2 (nc) 6059 3 sync 5922 4 frs 5786 5 fr 5649 6 cl 5513 7 dof 5376 8 sync 5240 9v ss 5103 10 cs1 4967 11 cs2 4830 12 v dd 4694 13 res 4557 14 a0 4421 15 v ss 4284 16 wr,r/w 4148 17 rd, e 4011 18 v dd 3875 19 d0 3738 20 d1 3602 21 d2 3465 22 d3 3329 23 d4 3192 24 d5 3056 25 d6 (scl) 2919 26 d7 (si) 2783 27 v dd 2646 28 v dd 2512 29 v dd 2378 30 v dd 2245 31 v dd 2111 32 v ss 1977 33 v ss 1843 34 v ss 1709 35 v ss2 1575 36 v ss2 1441 37 v ss2 1307 38 v ss2 1173 39 v ss2 1039 40 (nc) 906 41 v out 772 42 v out 638 43 cap3 C 504 44 cap3 C 370 45 (nc) 236 46 cap1+ 102 47 cap1+ C 32 48 cap1 CC 166 49 cap1 CC 300 50 cap2 CC 433 pad pin xy no. name 51 cap2 CC 567 1246 52 cap2+ C 701 53 cap2+ C 835 54 v ss C 969 55 v ss C 1103 56 v rs C 1237 57 v rs C 1371 58 v dd C 1505 59 v dd C 1639 60 v 1 C 1772 61 v 1 C 1906 62 v 2 C 2040 63 v 2 C 2174 64 (nc) C 2308 65 v 3 C 2442 66 v 3 C 2576 67 v 4 C 2710 68 v 4 C 2844 69 v 5 C 2978 70 v 5 C 3111 71 (nc) C 3245 72 v r C 3379 73 test1 C 3513 74 test2 C 3647 75 test3 C 3781 76 test4 C 3915 77 v dd C 4049 78 m/s C 4185 79 cls C 4322 80 v ss C 4458 81 c86 C 4595 82 p/s C 4731 83 v dd C 4868 84 hpm C 5004 85 v ss C 5141 86 irs C 5277 87 v dd C 5414 88 test5 C 5550 89 test6 C 5687 90 test7 C 5836 91 test8 C 5956 92 test9 C 6076 93 (nc) C 6195 94 (nc) C 6474 1248 95 com15 1163 96 com15 1090 97 com14 1017 98 com14 945 99 com13 872 100 com13 799 pad pin xy no. name 101 com12 C 6474 727 102 com12 654 103 com11 581 104 com11 509 105 com10 436 106 com10 363 107 com9 291 108 com9 218 109 com8 145 110 com8 73 111 com7 0 112 com7 C 73 113 com6 C 145 114 com6 C 218 115 com5 C 291 116 com5 C 363 117 com4 C 436 118 com4 C 509 119 com3 C 581 120 com3 C 654 121 com2 C 727 122 com2 C 800 123 com1 C 872 124 com1 C 945 125 com0 C 1018 126 com0 C 1090 127 coms C 1163 128 (nc) C 1248 129 (nc) C 6232 C 1246 130 (nc) C 6147 131 (nc) C 6075 132 seg0 C 6002 133 seg1 C 5930 134 seg2 C 5859 135 seg3 C 5787 136 seg4 C 5715 137 seg5 C 5643 138 seg6 C 5571 139 seg7 C 5499 140 seg8 C 5427 141 seg9 C 5355 142 seg10 C 5283 143 seg11 C 5212 144 seg12 C 5140 145 seg13 C 5068 146 seg14 C 4996 147 seg15 C 4924 148 seg16 C 4852 149 seg17 C 4780 150 seg18 C 4708
S1D15705 series technical manual 12 epson rev. 3.2 unit: m pad pin xy no. name 151 seg19 C 4636 C 1246 152 seg20 C 4564 153 seg21 C 4493 154 seg22 C 4421 155 seg23 C 4349 156 seg24 C 4277 157 seg25 C 4205 158 seg26 C 4133 159 seg27 C 4061 160 seg28 C 3989 161 seg29 C 3917 162 seg30 C 3846 163 seg31 C 3774 164 seg32 C 3702 165 seg33 C 3630 166 seg34 C 3558 167 seg35 C 3486 168 seg36 C 3414 169 seg37 C 3342 170 seg38 C 3270 171 seg39 C 3199 172 seg40 C 3127 173 seg41 C 3055 174 seg42 C 2983 175 seg43 C 2911 176 seg44 C 2839 177 seg45 C 2767 178 seg46 C 2695 179 seg47 C 2623 180 seg48 C 2552 181 seg49 C 2480 182 seg50 C 2408 183 seg51 C 2336 184 seg52 C 2264 185 seg53 C 2192 186 seg54 C 2120 187 seg55 C 2048 188 seg56 C 1976 189 seg57 C 1905 190 seg58 C 1833 191 seg59 C 1761 192 seg60 C 1689 193 seg61 C 1617 194 seg62 C 1545 195 seg63 C 1473 196 seg64 C 1401 197 seg65 C 1329 198 seg66 C 1258 199 seg67 C 1186 200 seg68 C 1114 pad pin xy no. name 201 seg69 C 1042 C 1246 202 seg70 C 970 203 seg71 C 898 204 seg72 C 826 205 seg73 C 754 206 seg74 C 682 207 seg75 C 611 208 seg76 C 539 209 seg77 C 467 210 seg78 C 395 211 seg79 C 323 212 seg80 C 251 213 seg81 C 179 214 seg82 C 107 215 seg83 C 35 216 seg84 36 217 seg85 108 218 seg86 180 219 seg87 252 220 seg88 324 221 seg89 396 222 seg90 468 223 seg91 540 224 seg92 612 225 seg93 683 226 seg94 755 227 seg95 827 228 seg96 899 229 seg97 971 230 seg98 1043 231 seg99 1115 232 seg100 1187 233 seg101 1259 234 seg102 1330 235 seg103 1402 236 seg104 1474 237 seg105 1546 238 seg106 1618 239 seg107 1690 240 seg108 1762 241 seg109 1834 242 seg110 1906 243 seg111 1977 244 seg112 2049 245 seg113 2121 246 seg114 2193 247 seg115 2265 248 seg116 2337 249 seg117 2409 250 seg118 2481 pad pin xy no. name 251 seg119 2553 C 1246 252 seg120 2625 253 seg121 2696 254 seg122 2768 255 seg123 2840 256 seg124 2912 257 seg125 2984 258 seg126 3056 259 seg127 3128 260 seg128 3200 261 seg129 3272 262 seg130 3343 263 seg131 3415 264 seg132 3487 265 seg133 3559 266 seg134 3631 267 seg135 3703 268 seg136 3775 269 seg137 3847 270 seg138 3919 271 seg139 3990 272 seg140 4062 273 seg141 4134 274 seg142 4206 275 seg143 4278 276 seg144 4350 277 seg145 4422 278 seg146 4494 279 seg147 4566 280 seg148 4637 281 seg149 4709 282 seg150 4781 283 seg151 4853 284 seg152 4925 285 seg153 4997 286 seg154 5069 287 seg155 5141 288 seg156 5213 289 seg157 5284 290 seg158 5356 291 seg159 5428 292 seg160 5500 293 seg161 5572 294 seg162 5644 295 seg163 5716 296 seg164 5788 297 seg165 5860 298 seg166 5931 299 seg167 6003 300 (nc) 6075
S1D15705 series technical manual rev. 3.2 epson 13 unit: m pad pin xy no. name 301 (nc) 6147 C 1246 302 (nc) 6232 C 1248 304 seg168 C 1163 305 seg169 C 1090 306 seg170 C 1018 307 seg171 C 945 308 seg172 C 872 309 seg173 C 800 310 seg174 C 727 311 seg175 C 654 312 seg176 C 581 313 seg177 C 509 314 seg178 C 436 315 seg179 C 363 316 seg180 C 291 317 seg181 C 218 318 seg182 C 145 319 seg183 C 73 320 seg184 0 321 seg185 73 322 seg186 145 323 seg187 218 324 seg188 291 325 seg189 363 326 seg190 436 327 seg191 509 328 seg192 581 329 seg193 654 330 seg194 727 331 seg195 799 332 seg196 872 333 seg197 945 334 seg198 1017 335 seg199 1090 336 coms 1163 337 (nc) 1248
S1D15705 series technical manual 14 epson rev. 3.2 pin name i/o description number of pins v dd power commonly used with the mpu power supply pin v cc .12 supply v ss power 0 v pin connected to the system ground (gnd). 9 supply v ss2 power boosting circuit reference power supply for liquid crystal drive. 5 supply v rs power external input pin for liquid crystal power supply voltage supply adjusting circuit. 2 they are set to open. v 1 , v 2 power multi-level power supply for liquid crystal drive. the voltage 10 v 3 , v 4 supply specified according to liquid crystal cells is impedance-converted v 5 by a split resistor or operation amplifier (op amp) and applied. the potential needs to be specified based on v dd to establish the relationship of dimensions shown below: v dd (=v 0 ) lcd power supply circuit pin pin name i/o description number of pins cap1+ o boosting capacitor positive side connecting pin. connects 2 a capacitor between the pin and cap1 C pin. cap1 C o boosting capacitor negative side connecting pin. connects 2 a capacitor between the pin and cap1+ pin. cap2+ o boosting capacitor positive side connecting pin. connects 2 a capacitor between the pin and cap2 C pin. cap2 C o boosting capacitor negative side connecting pin. connects 2 a capacitor between the pin and cap2+ pin. cap3 C o boosting capacitor negative side connecting pin. connects 2 a capacitor between the pin and cap1+ pin. v out o boosting output pin. connects a capacitor between the pin and v ss2 .2 v r i voltage adjusting pin. applies voltage between v dd and v 5 using 1 a split resistor. valid only when the v 5 voltage adjusting built-in resistor is not used (irs=low) do not use vr when the v 5 voltage adjusting built-in resistor is used (irs=high) 5. pin description power supply pin S1D15705 *** s1d15707 *** , s1d15708 *** v 1 1/9 ? v 5 1/7 ? v 5 1/6 ? v 5 1/5 ? v 5 v 2 2/9 ? v 5 2/7 ? v 5 2/6 ? v 5 2/5 ? v 5 v 3 7/9 ? v 5 5/7 ? v 5 4/6 ? v 5 3/5 ? v 5 v 4 8/9 ? v 5 6/7 ? v 5 5/6 ? v 5 4/5 ? v 5
S1D15705 series technical manual rev. 3.2 epson 15 system bus connecting pins pin name i/o description number of pins d7 to d0 i/o an 8-bit bidirectional data bus is used to connect an 8-bit or 16-bit 8 (si) standard mpu data bus. (scl) when the serial interface is selected (p/s=low), d7: serial data entry pin (si) d6: serial clock input pin (scl) in this case, d0 to d5 are set to high impedance. when chip select is in the non-active state, d0 to d7 are set to high impedance. a0 i normally the lowest order bit of the mpu address bus is connected 1 to discriminate data / commands. a0=high: indicates that d0 to d7 are display data. a0=low: indicates that d0 to d7 are control data. res i initialized by setting res to low. 1 reset operation is performed at the res signal level. cs1 i chip select signal. when cs1=low and cs2=high, this signal 2 cs2 becomes active and the input/output of data/commands is enabled. rd i ? when the 80 series mpu is connected, active low is set. 1 (e) pin that connects the rd signal of the 80 series mpu. when this signal is low, the S1D15705 series data bus is set in the output state. ? when the 68 series mpu is connected, active high is set. 68 series mpu enable clock input pin wr i ? when the 80 series mpu is connected, active low is set. 1 (r/w) pin that connects the wr signal of the 80 series mpu. the data bus signal is latched on the leading edge of the wr signal. ? when the 68 series mpu is connected, read/write control signal input pin r/w=high: read operation r/w=low: write operation frs o output pin for static drive 1 used together with the sync pin c86 i mpu interface switching pin 1 c86=high: 68 series mpu interface c86=low: 80 series mpu interface p/s i switching pin for parallel data entry/serial data entry 1 p/s=high: parallel data entry p/s=low: serial data entry according to the p/s state, the following table is given. when p/s=low, d0 to d5 are set to high impedance. d0 to d5 can be high, low, or open . rd(e) and wr (r/w) are fixed to high or low. for the serial data entry, ram display data cannot be read. p/s data/ data read/write serial clock command high a0 d0 to d7 rd, wr low a0 si (d7) write-only scl (d6)
S1D15705 series technical manual 16 epson rev. 3.2 pin name i/o description number of pins cls i pin that selects the validity/invalidity of the built-in oscillator circuit 1 for display clocks. cls=high: built-in oscillator circuit valid cls=low: built-in oscillator circuit invalid (external input) when cls=low, display clocks are input from the cl pin. when the S1D15705 series is used for the master/slave configuration, each of the cls pins is set to the same level together. m/s i pin that selects the master/slave operation for the S1D15705 series. 1 the liquid crystal display system is synchronized by outputting the timing signal required for the liquid crystal display for the master operation and inputting the timing signal required for the liquid crystal display for the slave operation. m/s=high : master operation m/s=low : slave operation according to the m/s and cls states, the following table is given. cl i/o display clock i/o pin 1 according to the m/s and cls states, the following table is given. when the S1D15705 series is used for the master/slave configuration, each cl pin is connected. fr i/o liquid crystal alternating current signal i/o pin 1 m/s=high : output m/s=low : input when the S1D15705 series is used for the master/slave configuration, each fr pin is connected. sync i/o liquid crystal synchronizing current signal i/o pin 2 m/s=high : output m/s=low : input when the S1D15705 series is used for the master/slave configuration, each sync pin is connected. dof i/o liquid crystal display blanking control pin 1 m/s=high : output m/s=low : input when the S1D15705 series is used for the master/slave configuration, each dof pin is connected. irs i v 5 voltage adjusting resistor selection pin 1 irs=high: built-in resistor used irs=low: built-in resistor not used. the v 5 voltage is adjusted by the vr pin and stand-alone split resistor. valid only at master operation. the pin is fixed to high or low at slave operation. hpm i power supply control pin of the power supply circuit for liquid 1 crystal drive hpm=high : normal mode hpm=low : high power supply mode valid only at master operation. the pin is fixed to high or low at slave operation. m/s cls cl high high output low input low high input low input display clock master slave built-in oscillator circuit used high high external input low low m/s cls oscillator power supply cl fr sync frs dof circuit circuit high high valid valid output output output output output low invalid valid input output output output output low high invalid invalid input input input output input low invalid invalid input input input output input
S1D15705 series technical manual rev. 3.2 epson 17 liquid crystal drive pin pin name i/o description number of pins seg0 o output pins for the lcd segment drive. 168 or 200 to for the pin assignment by model, refer to the table below. segn contents of the display ram and fr signal are combined to select a desired level among v dd , v 2 , v 3 and v 5 . com0 output pins for the lcd common drive. 64 or 32 to for the pin assignment by model, refer to the table below. or 16 comn scan data and fr signal are combined to select a desired level among v dd , v 1 , v 4 and v 5 . coms o indicator dedicated com output pin. set to open when not used. 2 when coms is used for the master/slave configuration, the same signal is output to both the master and slave. test pin pin name i/o description number of pins test1 i/o ic chip test pin. fix the pin to high. 6 to 6 when using the temperature sensor with the S1D15705 * 10 ** , refer to section 17. temperature sensor circuit . test7 i/o ic chip test pin. take into consideration so that the capacity of 3 to 9 lines cannot be exhausted by setting the pin to open. output voltage ram data fr display display reversal normal operation high high v dd v 2 high low v 5 v 3 low high v 2 v dd low low v 3 v 5 power save v dd product name seg number of pins S1D15705 ***** seg0 to seg167 168 s1d15707 ***** /s1d15708 ***** seg0 to seg199 200 scanning data fr output voltage high high v 5 high low v dd low high v 1 low low v 4 power save v dd product name seg number of pins S1D15705 ***** com0 to com63 64 s1d15707 ***** com0 to com31 32 s1d15708 ***** com0 to com15 16
S1D15705 series technical manual 18 epson rev. 3.2 6. function description mpu interface selection of interface type the S1D15705 series transfers data through 8-bit bidirectional data buses (d7 to d0) or serial data input (si). by setting the polarity of the p/s pin to either high or low, the 8-bit parallel data entry or serial data entry can be selected as listed in table 1. table 1 p/s cs1 cs2 a0 rd wr c86 d7 d6 d5 to d0 high: parallel data entry cs1 cs2 a0 rd wr c86 d7 d6 d5 to d0 low: serial data entry cs1 cs2 a0 si scl (hz) fix ?to high or low. hz indicates the high impedance state. parallel interface when the parallel interface is selected (p/s=high), the S1D15705 series can directly be connected to the mpu bus of either the 80 or 68 series mpu by setting the c86 pin to high or low as listed in table 2. table 2 c86 cs1 cs2 a0 rd wr d7 to d0 h: 68 series mpu bus cs1 cs2 a0 e r/w d7 to d0 l: 80 series mpu bus cs1 cs2 a0 rd wr d7 to d0 in addition, the data bus signal can be identified according to the combinations of the a0, rd (e), wr (r/w) signals as listed in table 3. table 3 common 68 series 80 series a0 r/w rd wr function 1 1 0 1 display data read 1 0 1 0 display data write 0 1 0 1 status read 0 0 1 0 control data write (command)
S1D15705 series technical manual rev. 3.2 epson 19 chip select the S1D15705 series has two chip select pins cs1 and cs2 and enables the mpu interface or serial interface only when cs1=low and cs2=high. when chip select is in the non-active state, d0 to d7 are in the high impedance state and the a0, rd, and wr inputs become invalid. when the serial interface is selected, the shift register and counter are reset. display data ram and internal register access since the S1D15705 series access viewed from the mup side satisfies the cycle time and does not require the wait time, high-speed data transfer is enabled. the S1D15705 series performs a kind of inter-lsi pipeline processing through the bus holder attached to the internal data bus when it performs the data transfer with the mpu. for example, when data is written on the display data ram, the data is first held in the bus holder and written serial interface when the serial interface is selected (p/s=low), the serial data entry (si) and serial clock input(scl) can be accepted with the chip in the non-active state (cs1=low or cs2=high. the serial interface consists of an 8-bit shift register and a 3-bit counter. serial data is fetched from the serial data entry pin in the order of d7, d6, ...., and d0 on the leading edge of the serial clock and converted into 8-bit parallel data on the leading edge of the 8th serial clock, then processed. whether to identify that the serial data entry is display data or command is judged by the a0 input, and a0=high indicates display data and a0=low indicates the command. after the chip is set to the non-active state, the a0 input is read and identified at the timing on the 8 n-th leading edge of the serial clock. fig. 1 shows the signal chart of the serial interface. on the display data ram up to the next data write cycle. further, when the mpu reads the contents of display data ram, the read data at the first data read cycle (dummy) is held in the bus holder and read on the system bus from the bus holder up to the next data read cycle. the read sequence of the display data ram is restricted. when the address is set, note that the specified address data is not output to the subsequent read instruction and output at the second data read. therefore single dummy read is required after the address set and write cycle. fig. 2 shows this relationship. busy flag when the busy flag is ?? it indicates that the S1D15705 series is performing an internal operation, and only the status read instruction can be accepted. the busy flag is output to the d7 pin using the status read command. if the cycle time (t cyc ) is ensured, the mpu throughput can be improved greatly since this flag needs not be checked before each command. fig. 1 when the chip is in the non-active state, both the shift register and counter are reset to the initial state. cannot be read for the serial interface. for the scl signal, pay careful attention to the terminating reflection of lines and external noise. the operation confirmation using actual equipment is recommended. cs1 cs2 si scl a0 d7 1234567891011121314 d6 d5 d4 d3 d2 d7 d6 d5 d4 d3 d2 d1 d0
S1D15705 series technical manual 20 epson rev. 3.2 ?write n n n+1 n+2 n+3 n+1 n+2 n+3 wr mpu internal timing data latch bus holder write signal ?read n n n n+1 n+2 increment n+1 preset n n n n+1 n+2 data read #n+1 data read #n dummy read address set #n wr rd data address preset read signal column address bus holder mpu internal timing fig. 2
S1D15705 series technical manual rev. 3.2 epson 21 display data ram display data ram this display data ram stores display dot data and consists of 65 (8 pages one 8 bit + 1) 200 bits. desired bits can be accessed by specifying page and column addresses. since the mpu display data d7 to d0 correspond to the common direction of the liquid crystal display, the restrictions at display data transfer is reduced and the display configuration with the high degree of freedom can easily be obtained when the S1D15705 series is used for the multiple chip configuration. besides, the read/write operation to the display data ram is performed through the i/o buffer from the mpu side independently of the liquid crystal drive signal read. therefore even when the display data ram is asynchronously accessed during liquid crystal display, the access will not have any adverse effect on the display such as flickering. page address circuit as shown in fig. 4, the page address of the display data ram is specified using the page address set command. to access the data using a new page, the page address is respecified. the page address 8 (d3,d2,d1,d0=1,0,0,0) is an indicator dedicated ram area and only the display data d0 is valid. column address circuit as shown in fig. 4, an address on the column side of the display data ram is specified using the column address set command. since the specified address is incremented by 1 whenever the display data read/write command is input, the mpu can successively access the display data. besides, the column address stops the increment at the column c7h. since the column and page addresses are independent each other, for example, the page and column addresses need to be respecified respectively to move from the column c7h of page 0 and column 00h. further, as shown in fig. 4, the correspondence relationship between the column address of the display data ram and the segment address can be reversed using the adc command (segment driver direction select command). therefore the ic assignment restrictions at lcd module assembly are reduced. fig. 3 d0 d1 d2 d3 d4 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 display data ram com0 com1 com2 com3 com4 liquid crystal display S1D15705 ***** s1d15707 ***** / s1d15708 ***** seg output seg0 seg167 seg0 seg199 adc 0 0 (h) 1 c7 (h) line address circuit when displaying contents of the display data ram, the line address circuit is used for specifying the corresponding addresses. see figure 4-1 and 4-2. using the display start line address set command, the top line is normally selected (when the common output state is normal, com0 is output. and, when reversed, the S1D15705 ***** outputs com63, s1d15707 ***** outputs com31 and table 4 s1d15708 ***** outputs com15). for the S1D15705 ***** , the display area of 65 lines is secured starting from the specified display start line address in the address incrementing direction. and, 33 lines are provided for the s1d15707 ***** , 17 lines are provided for the s1d15708 ***** . dynamically changing the line address using the display start line address set command enables screen scrolling and page change.
S1D15705 series technical manual 22 epson rev. 3.2 fig. 4-1 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 coms 0 0 0 0 page 0 0 0 0 1 page 1 0 0 1 0 page 2 0 0 1 1 page 3 0 1 0 0 page 4 0 1 0 1 page 5 0 1 1 0 page 6 0 1 1 1 page 7 1000 page 8 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 c7 c6 c5 c4 c3 c2 c1 c0 00 01 02 03 04 05 06 07 seg160 seg161 seg162 seg163 seg164 seg165 seg166 seg167 27 26 25 24 23 22 21 20 a0 a1 a2 a3 a4 a5 a6 a7 lcd out adc column address 1 d0 0 d0 63 lines page address d3 d2 d1 d0 data line address com output common output state: normal rotation S1D15705 ***** : when setting the display start line to one channel start the 65th line is accessed independently of the display start line address.
S1D15705 series technical manual rev. 3.2 epson 23 fig. 4-2 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 coms 0 0 0 0 page 0 0 0 0 1 page 1 0 0 1 0 page 2 0 0 1 1 page 3 0 1 0 0 page 4 0 1 0 1 page 5 0 1 1 0 page 6 0 1 1 1 page 7 1000 page 8 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 c7 c6 c5 c4 c3 c2 c1 c0 00 01 02 03 04 05 06 07 seg192 seg193 seg194 seg195 seg196 seg197 seg198 seg199 07 06 05 04 03 02 01 00 c0 c1 c2 c3 c4 c5 c6 c7 lcd out adc column address 1 d0 0 d0 the 33rd of s1d15707 ***** and the 17th s1d15708 ***** are accessed independ-ently of the display start line address. 16 lines page address d3 d2 d1 d0 data line address com output common output state: normal rotation start 32 lines start s1d15707 ***** , s1d15708 ***** : when setting the display start line to one channel
S1D15705 series technical manual 24 epson rev. 3.2 display data latch circuit the display data latch circuit is a latch that temporarily stores the display data output from the display data ram to the liquid crystal drive circuit. since the display normal rotation/reversal, display on/off, and display all lighting on/off commands control the data in this latch, the data within the display data ram is not changed. oscillator circuit this oscillator circuit is a cr type oscillator and generates display clocks. the oscillator circuit is valid only when m/s=high and cls=high and starts oscillation after the built-in oscillator circuit on command is entered. when cls=low, the oscillation is stopped and the display clocks are entered from the cl pin. display timing generator circuit this display timing generator circuit generates timing signals from the display clocks to the line address circuit and the display latch circuit. it latches the display data to the display data latch circuit and outputs it to the segment drive output pin by synchronizing to the display clocks. the read operation of display data to the liquid crystal drive circuit is completely independent of the access to the display data ram from the mpu. therefore even when the display data ram is asynchronously accessed during liquid crystal display, the access will not have any adverse effect on the display such as flickering. the circuit also generates the internal common timing, liquid crystal alternating current signal (fr), and synchronous signal (sync) from the display clocks. as shown in fig. 5 and 6, the fr normally generates the drive waveforms in the 2-frame alternating current drive system to the liquid crystal drive circuit. it can generate n-line reversal alternating current drive waveforms by setting data (n-1) to the n-line reversal drive register. if a display quality problem such as crosstalk occurs, it can be improved by using the n-line reversal alternating current drive waveforms. determine the number of lines (n) to which alternating current is applied by actually displaying the liquid crystal. snyc is a signal that synchronizes the line counter and common timing generator circuit to the sync signal output side ic. therefore the sync signal becomes a waveform at a duty ratio of 50% that synchronizes to the frame synchronization. when the S1D15705 series is used for the multiple chip configuration, the slave side needs to supply the display timing signals (fr, sync, cl, and dof) from the master side. table 5 shows the state of fr, sync, cl, or dof. 2-frame alternating current drive waveforms fig. 5 64 cl sync fr com0 v dd v dd v dd v 1 v 1 v 4 v 5 v 4 v 2 v 3 v 5 v 5 com1 ram data segn 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6 table 5 operation mode fr sync cl dof master (m/s=high) built-in oscillator circuit valid (cls=high) output output output output built-in oscillator circuit invalid (cls=low) output output input output slave (m/s=low) built-in oscillator circuit valid (cls=high) input input input input built-in oscillator circuit invalid (cls=low) input input input input
S1D15705 series technical manual rev. 3.2 epson 25 common output state selection circuit the S1D15705 series can set the scanning direction of the com output using the common output state selection command (see fig. 6). therefore the ic assignment restrictions at lcd module assembly are reduced. table 6 fig. 6 n-line reversal alternating current drive waveforms (example of n=5: when the line reversal register is set to 4) 64 cl sync fr com0 v dd v dd v dd v 1 v 1 v 4 v 5 v 4 v 2 v 3 v 5 v 5 com1 ram data segn 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6 liquid crystal drive circuit these are a 233-channel (S1D15705 ***** and s1d15707 ***** ), a 217-channel (s1d15708 ***** ) multiplexers that generate four voltage levels for liquid crystal drive. it outputs the liquid crystal drive voltage that corresponds to the combinations of the display data, com scanning signal, and fr signal. fig. 7 shows examples of the seg and com output waveforms. state com scanning direction S1D15705 ***** s1d15707 ***** s1d15708 ***** normal rotation com 0
S1D15705 series technical manual 26 epson rev. 3.2 fig. 7 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 fr com0 com1 com2 seg0 seg1 seg2 com0 C seg0 com0 C seg1 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 5 v 4 v 3 C v 3 C v 4 C v 5 v 2 v 1 v dd C v 1 C v 2 v 5 v 4 v 3 C v 3 C v 4 C v 5 v 2 v 1 v dd C v 1 C v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v ss
S1D15705 series technical manual rev. 3.2 epson 27 table 7 description of controlling bits using the power control set command item state ? ? d2 boosting circuit control bit on off d1 voltage adjusting circuit (v adjusting circuit) control bit on off d0 voltage follower circuit (v/f circuit) control bit on off table 8 reference combinations status of use d2 d1 d0 boosting v adjusting v/f external boosting circuit circuit circuit voltage input system pin 1 built-in power 1 1 1 o o o v ss2 used supply used 2 v adjusting circuit 0 1 1 x o o v out , v ss2 open and v/f circuit only 3 v/f circuit only 0 0 1 x x o v 5 , v ss2 open 4 external power 0 0 0 x x x v 1 to v 5 open supply only the boosting system pin indicates the cap1+, cap1? cap2+, cap2? or cap3?pin. although the combinations other than those listed in the above table are also possible, they cannot be recommended because they are not actual use methods. power supply circuit this power supply circuit is a low power supply consumption one that generates the voltage required for the liquid crystal drive and consists of a boosting circuit, voltage adjusting circuit, and voltage follower circuit. it is valid only at master operation. the power supply circuit on/off controls the boosting circuit, voltage adjusting circuit, and voltage follower circuit using the power supply control set command, respectively. therefore, it can also use the partial functions of the external power supply and built-in power supply together. table 7 lists the functions that control 3-bit data using the power control set command and table 8 lists the reference combinations. boosting circuit the boosting circuit incorporated in the S1D15705 series enables the quadruple boosting, triple boosting, and double boosting of the v dd ?v ss2 potential. for the quadruple boosting, the v dd ? v ss2 potential is quadruple-boosted to the negative side and output to the v out pin by connecting the capacitor c1 between cap1+ ? and cap1? between cap2+ ? and cap2? between cap1+ ? and cap3? and between v ss2 ? and v out . for the triple boosting, the v dd ? v ss2 potential is triple-boosted to the negative side and output to the v out pin by connecting the capacitor c1 between cap1+ ? and cap1? between cap2+ ? and cap2? and between v ss2 ? and v out and strapping both cap3?and v out pins. for the double boosting, the v dd ? v ss2 potential is doubly boosted to the negative side and output to the v out pin by connecting the capacitor c1 between cap1+ ? and cap1? and between v ss2 ? , setting cap2+ to open, and v out and strapping cap2? cap3? and v out pins. fig. 8 shows the relationships of boosting potential.
S1D15705 series technical manual 28 epson rev. 3.2 voltage adjusting circuit the boosting voltage generated in v out outputs the liquid crystal drive voltage v 5 through the voltage adjusting circuit. since the S1D15705 series incorporates a high-accuracy constant power supply, 64-step electronic control function, and v 5 voltage adjusting resistor, a high- accuracy voltage adjusting circuit can eliminate and save parts. (a) when using the v 5 voltage adjusting built-in resistor the liquid crystal power supply voltage v 5 can be controlled only using the command without an external resistor and the light and shade of liquid crystal display be adjusted by using the v 5 voltage adjusting built-in resistor and the electronic control function. the v 5 voltage can be obtained according to expression a-1 within the range of |v 5 |<|v out |. (expression a-1) v rb ra v rb ra v vv ev reg ev reg 5 1 11 162 1 162 =+ ? ? ? ? ? =+ ? ? ? ? ? ? ? ? ? ? =? () ? [] q fig. 8 set the v ss2 ?voltage range so that the voltage of the v out pin cannot exceed the absolute maximum ratings. v ss2 v out cap3 C cap1+ cap1 C cap2 C cap2+ c1 c1 c1 c1 + + + S1D15705 series quadruple boosting circuit v ss2 v out cap3 C cap1+ cap1 C cap2 C cap2+ c1 c1 c1 + + + S1D15705 series triple boosting circuit v ss2 v out cap3 C cap1+ cap1 C cap2 C cap2+ open c1 c1 + + S1D15705 series double boosting circuit v dd = 0v v ss2 = C 3v v out = 4 x v ss2 = C 12v quadruple boosting potential relationship v dd = 0v v ss2 = C 3v v out = 3 x v ss2 = C 9v triple boosting potential relationship v dd = 0v v ss2 = C 5v v out = 2 x v ss2 = C 10v double boosting potential relationship
S1D15705 series technical manual rev. 3.2 epson 29 v reg is a constant voltage source within an ic, and the value at ta=25 c is constant as listed in table 9. table 9 device temperature unit v reg unit gradient internal C 0.05 [%/ C 2.1 [v] power supply indicates an electronic control command value. setting data in a 6-bit electronic control register enters one state among 64 states. table 10 lists the values of based on the setup of the electronic control register. table 10 d5 d4 d3 d2 d1 d0 111101 2 111110 1 111111 0 rb/ra indicates the v 5 voltage adjusting built-in resistance ratio and can be adjusted into eight steps using the v 5 voltage adjusting built-in resistance ratio set command. the reference values of the (1+rb/ra) ratio are obtained as listed in table 11 by setting 3-bit data in the v 5 voltage adjusting built-in resistance ratio register. table 11 (reference values) fig. 9 v ev (constant voltage source + electronic control) built-in ra + C built-in rb v dd v 5 S1D15705 ***** s1d15707 ***** / s1d15708 ***** register device per temperature device per temperature gradient [unit: %/ c] gradient [unit: %/ c] d2 d1 d0 ?.05 ?.05 0 0 0 4.5 3.0 0 0 1 5.0 3.5 0 1 0 5.5 4.0 0 1 1 6.0 4.5 1 0 0 6.5 5.0 1 0 1 7.0 5.5 1 1 0 7.6 6.0 1 1 1 8.1 6.5 it is necessary to take a manufacturing deviation of upto 7% of the built-in resistance ratio into consideration. when this is not permissible, supplement external ra and rb to ajdust the v 5 voltage. figs. 10 show the v 5 voltage reference values per temperature gradient device based on the values of the v 5 voltage adjusting built-in resistance ratio register and electronic control register at ta=25 c.
S1D15705 series technical manual 30 epson rev. 3.2 fig. 10-1 S1D15705 ***** C 0.05%/ C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 0 v 5 [v] 00h 18h 30h 3fh electric volume resister 111 S1D15705 ***** 000 001 010 011 100 101 110 v 5 voltage adjusting built-in resistance ratio registers (d2, d1, and d0) fig. 10-2 s1d15707 ***** , s1d15708 ***** C 0.05%/ C v dd = C 10v or v 5 C v dd =less than C 10v) C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 0 v 5 [v] 00h 18h 30h 3fh electric volume resister 111 s1d15707 ***** , s1d15708 ***** 000 001 010 011 100 101 110 v 5 voltage adjusting built-in resistance ratio registers (d2, d1, and d0)
S1D15705 series technical manual rev. 3.2 epson 31 (b) when using the external resistor (not using the v 5 voltage adjusting built-in resistor) 1 the liquid crystal power supply voltage v 5 can also be set by adding the resistors (ra and rb ) between v dd and v r and between v r and v 5 without the v5 voltage adjusting built-in resistor (irs pin=low). also in this case, the liquid crystal power supply voltage v 5 can be controlled using the command and the light and shade of liquid crystal display can be adjusted by using the electronic control function. the v 5 voltage can be obtained from expression b- 1 by setting the external resistors ra and rb within the range of |v 5 | < |v out |. (expression b-1) set the value of the electronic control register as the intermediate value (d5, d4, d3, d2, d1, d0) = (1,0,0,0,0,0). from the foregoing we can establish the expression: from expression b-1, it follows that (expression b-2) also, suppose the current applied to ra and rb is 5 a. (expression b-2) it follows that therefore from expressions b-2 and b-3, we have in this case, table 14 lists the v 5 voltage variable range and pitch width using the electronic control function. = = 31 21 vv reg . v rb ra v v rb ra reg 5 11 162 71 1 31 162 21 =+ ? ? ? ? ?? ? ? ? ? ? ?=+ ? ? ? ? ?? ? ? ? ? ?? () ' ' ' ' . ra rb m ''. += 14 ? rb ra ra k rb k ' ' . ' ' = =? =? 312 340 1060 v rb ra v rb ra v vv ev reg ev reg 5 1 11 162 1 162 =+ ? ? ? ? ? =+ ? ? ? ? ? ? ? ? ? ? =? () ? [] ' ' ' ' q v ev (constant voltage source + electronic control) v r stand-alone ra' + C stand-alone rb v dd v 5 fig. 11 S1D15705 ***** when setting v 5 = C 9 v at ta=25 from fig. 8 and expression a-1. table 12 register description d5 d4 d3 d2 d1 d0 v 5 voltage adjusting CCC 010 electronic control 0 1 1 0 0 1 in this case, table 13 lists the v 5 voltage variable range and pitch width using the electronic control function. table 13 v 5 min. typ. max. unit variable range C 11.6 to C 9.3 to C 7.1 [v] pitch width 67 [mv] S1D15705 ***** when setting v 5 = C 7 v at ta=25
S1D15705 series technical manual 32 epson rev. 3.2 (c) when using the external resistor (not using the v 5 voltage adjusting built-in resistor) 2 in the use of the above-mentioned external resistor, the liquid crystal power supply voltage v 5 can also be set by adding the resistors to finely adjust ra and rb . also in this case, the liquid crystal power supply voltage v 5 can be controlled using the command and the light and shade of liquid crystal display can be adjusted by using the electronic control function. the v 5 voltage can be obtained from the following expression c-1 by setting the external resistors r 1 , r 2 (variable resistors), and r 3 within the range of |v 5 | < |v out | and finely adjusting r 2 ( ? r 2 ). (expression c-1) set the value of the electronic control register as the intermediate value (d5, d4, d3, d2, d1, d0) = (1,0,0,0,0,0). from the foregoing we can establish the expression: = =? 31 21 vv reg . when ? r 2 =0 ? , to obtain v 5 = 9 v from expression c- 1, it follows that ?=+ + ? ? ? ? ? ? ?? ? ? ? ? ?? () 91 1 31 162 21 32 1 v rr r . (expression c-2) when ? r2=r2, to obtain v 5 =-5v, it follows that ?=+ + ? ? ? ? ? ? ?? ? ? ? ? ?? () 51 1 31 162 21 3 12 v r rr . (expression c-3) also, suppose the current applied between v dd and v 5 is 5 a. rr r m 123 14 ++= ? . (expression c-4) it follows that therefore from expressions c-2, c-3, and c-4, we have rk rk rk 1 2 3 264 211 925 =? =? =? v rr r rr v rr r rr v vv ev reg ev reg 5 32 2 12 32 2 12 1 11 162 1 162 =+ +? +? ? ? ? ? ? ? ? =+ +?? +? ? ? ? ? ? ? ? ? ? ? ? ? =? () ? [] ? q fig. 12 S1D15705 ***** when setting v 5 = C 5 to C 9 v at ta=25 ? C v dd v 5 rb' ra' stand-alone r2 stand-alone r2 table 14 v 5 min. typ. max. unit variable range C 8.6 to C 7.0 to C 5.3 [v] pitch width 52 [mv]
S1D15705 series technical manual rev. 3.2 epson 33 in this case, table 6-15 lists the v 5 voltage variable range and pitch width using the electronic control function. table 15 v 5 min. typ. max. unit variable range C 8.7 to C 7.0 to C 5.3 [v] pitch width 53 [mv] when using the v 5 voltage adjusting built-in resistor or electronic control function, the state where at least the voltage adjusting circuit and voltage follower circuit are operated together needs to be set using the power control set command. also when the boosting circuit is off, the voltage needs to be applied from v out . the v r pin is valid only when the v 5 voltage adjusting built-in resistor (irs pin=low). set the v r pin to open when using the v 5 voltage adjusting built-in resistor (irs pin=high). since the v r pin has high input impedance, noise must be taken into consideration such as for short and shielded lines. liquid crystal voltage generator circuit the v 5 voltage is resistor-split within an ic and generates the v 1 , v 2 , v 3 , and v 4 potentials required for the liquid crystal drive. further, the v 1 , v 2 , v 3 , and v 4 potentials are impedance- converted by the voltage follower and supplied to the liquid crystal drive circuit. using the bias set command allows you to select a desired bias ratio from 1/9 or 1/7 for the S1D15705 ***** and 1/6 or 1/5 for the s1d15707 ***** and s1d15708 ***** . high power mode the power supply circuit incorporated in the S1D15705 series has the ultra-low power consumption (normal mode: hpm=high). therefore the display quality may be deteriorated in large load liquid crystal or panels. in this case, the display quality can be improved by setting hpm pin=low (high power mode). whether to use the power supply circuit in this mode should need the display confirmation by actual equipment. besides, if the improvement is insufficient even for the high power mode setting, the crystal liquid drive power needs to be supplied externally. command sequence when the built-in power supply is turned off to turn off the built-in power supply, set it in the power save state and then turn off the power supply according to the command sequence shown in fig. 13 (procedure). fig. 13 procedure step1 step2 description (command, state) power save turning off the built -in power supply command address d7 1 d6 0 d5 1 d4 0 power save command (both stand-by and sleep can be useal ) d3 1 d2 0 d1 0 d0 0 1
S1D15705 series technical manual 34 epson rev. 3.2 reference circuit examples v dd v dd v dd v ss c 1 v ss2 v out cap3 C cap1+ cap1 C cap2+ cap2 C v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s c 1 c 1 c 1 c 2 c 2 c 2 c 2 c 2 S1D15705 series v dd v ss c 1 v ss2 v out cap3 C cap1+ cap1 C cap2+ cap2 C v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s c 1 c 1 c 1 r 3 r 2 r 1 c 2 c 2 c 2 c 2 c 2 S1D15705 series (1) when using the v 5 voltage adjusting built-in resistor (example of v ss2 =v ss , quadruple boosting) 1 built-in power supply used (2) when not using the v 5 voltage adjusting built-in resistor (example of v ss2 =v ss , quadruple boosting) v dd v dd v ss v ss v out cap3 C cap1+ cap1 C cap2+ cap2 C v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s r 3 r 2 r 1 c 2 c 2 c 2 c 2 c 2 S1D15705 series (1) when using the v 5 voltage adjusting built-in resistor (2) when not using the v 5 voltage adjusting built-in resistor 2 only the voltage adjusting circuit and v/f circuit used external power supply external power supply v dd v dd v ss v ss cap3 C cap1+ cap1 C cap2+ cap2 C v out v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s c 2 c 2 c 2 c 2 c 2 S1D15705 series
S1D15705 series technical manual rev. 3.2 epson 35 item setting value unit c 1 1.0 to 4.7 *1 since the v r pin has high input impedance, it uses short and shielded wires. *2 c 1 and c 2 are determined according to the size of the lcd panel. set a value so that the liquid crystal drive voltage can be stable. [setting example] turn on the v adjusting circuit and the v/f circuit and apply external voltage. display lcd heavy load patterns like lateral stripes and determine c 2 so that the liquid crystal drive voltages (v 1 to v 5 ) can be stable. then turn on all built-in power supplies and determine c 1 . *3 capacity is connected in order to stabilize voltage between v dd and v ss power supplies. common reference setting example at v 5 = 8 to 12 v variable v dd v dd external power supply v ss v ss v out cap3 C cap1+ cap1 C cap2+ cap2 C v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s S1D15705 series 4 only the external power supply used depending on all external power supplies v dd v dd v ss external power supply v ss v out cap3 C cap1+ cap1 C cap2+ cap2 C v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s c 2 c 2 c 2 c 2 c 2 S1D15705 series 3 only the v/f circuit used
S1D15705 series technical manual 36 epson rev. 3.2 *4 when the built-in v/f circuit is used to drive an lcd panel with heavy alternating or direct current load, we recommend that external resistance be connected in order to stabilize v/f outputs, or electric potentials, v 1 , v 2 , v 3 and v 4 . fig. 15 v dd v dd v 1 v 2 v 3 v 4 v 5 r 4 r 4 r 4 r 4 c 2 c 2 S1D15705 series c 2 c 2 c 2 *5 precautions when installing the cog when installing the cog, it is necessary to duly consider the fact that there exists a resistance of the ito wiring occurring between the driver chip and the externally connected parts (such as capacitors and resistors). by the influence of this resistance, non-conformity may occur with the indications on the liquid crystal display. therefore, when installing the cog design the module paying sufficient considerations to the following three points. 1. suppress the resistance occurring between the driver chip pin to the externally connected parts as much as possible. 2. suppress the resistance connecting to the power supply pin of the driver chip. 3. make various cog module samples with different ito sheet resistance to select the module with the sheet resistance with sufficient operation margin. also, as for this driver ic, pay sufficient attention to the following points when connecting to external parts for the characteristics of the circuit. 1. connection to the boosting capacitors the boosting capacitors (the capacitors connecting to respective cap pins and capacitor being inserted between v out and v ss2 ) of this ic are being switched over by use of the transistor with very low on-resistance of about 10 ? . however, when installing the cog, the resistance of ito wiring is being inserted in series with the switching transistor, thus dominating the boosting ability. consequently, the boosting ability will be hindered as a result and pay sufficient attention to the wiring to respective boosting capacitors. 2. connection of the smoothing capacitors for the liquid crystal drive the smoothing capacitors for the liquid crystal driving potentials (v 1 . v 2 , v 3 and v 4 ) are indispensable for liquid crystal drives not only for the purpose of mere stabilization of the voltage levels. if the ito wiring resistance which occurs pursuant to installation of the cog is supplemented to these smoothing capacitors, the liquid crystal driving potentials become unstable to cause non- conformity with the indications of the liquid crystal display. therefore, when using the cog module, we definitely recommend to connect reinforcing resistors externally. reference value of the resistance is 100k ? to 1m ? . meanwhile, because of the existence of these reinforcing resistors, current consumption will increase. indicated below is an exemplary connection diagram of external resistors. please make sufficient evaluation work for the display statuses with any connection tests. v dd v dd v 1 v 2 v 3 v 4 v 5 r 4 r 4 c 2 c 2 S1D15705 series c 2 c 2 c 2 adjust resistance value r 4 to the optimal level by checking driving waveform displayed on the lcd. reference setting: r 4 = 0.1 to 1.0 [m ? ] exemplary connection diagram 1 for external resistance exemplary connection diagram 2 for external resistance
S1D15705 series technical manual rev. 3.2 epson 37 reset circuit when the res input is set to the low level, this lsi enters each of the initial setting states 1. display off 2. display normal rotation 3. adc select: normal rotation (adc command d0=0) 4. power control register: (d2,d1,d0)=(0,0,0) 5. register data clear within serial interface 6. lcd power supply bias ratio: S1D15705: 1/9 bias s1d15707/s1d15708: 1/6 bias 7. n-line alternating current reversal drive reset 8. sleeve mode cancel (standby mode is not canceled) 9. display all lighting off: (display all lighting on/off command d0=low) 10. built-in oscillator circuit stopped 11. static indicator off static indicator register: (d1,d2)=(0,0) 12. read modify write off 13. display start line set to the first line 14. column address set to address 0 15. page address set to page 0 16. common output state normal rotation 17. v 5 voltage adjusting built-in resistance ratio register: (d2,d1,d0)=(0,0,0) 18. electronic control register set mode reset electronic control register* (d5, d4, d3, d2, d1, d0) = (1,0,0,0,0,0) 19. n-line alternating current reversal register: (d3, d2, d1, d0) = (0, 0, 0, 0) 20. test mode reset on the other hand, when using the reset command, only the items 11 to 20 of the above-mentioned initial setting are executed. when the power is turned on, the initialization using the res pin is required. after the initialization using the res pin, each input pin needs to be controlled normally. besides, when the mpu control signal has high impedance, overcurrent may be applied to an ic. after turning on the power, take action so that the input pin cannot have high impedance. the S1D15705 series discharge electric charges of v 5 and v out at res pin is set to the low level. if external power supplies for driving lcd are used, do not input external power while the res pin is set to the low level to prevent short-circuiting between the external power supplies and v dd . exemplary connection diagram 1. exemplary connection diagram 2. v dd v dd v 1 v 2 v 3 v 4 v 5 r 4 r 4 r 4 r 4 c 2 c 2 S1D15705 series c 2 c 2 c 2 v dd v dd v 1 v 2 v 3 v 4 v 5 r 4 r 4 c 2 c 2 S1D15705 series c 2 c 2 c 2
S1D15705 series technical manual 38 epson rev. 3.2 7. command the S1D15705 series identifies data bus signals according to the combinations of a0, rd(e), and wr(r/w). since the interpretation and execution of commands are performed only by the internal timing independently of external clocks, the S1D15705 performs high-speed processing that does not require busy check normally. the 80 series mpu interface starts commands by inputting low pulses to the rd pin at read and to the wr pin at write operation. the 68 series mpu interface enters the read state when high is input to the r/w pin. it enters the write state when low is input to the same pin. it starts commands by inputting high pulses to the e pin (for the timing, see the timing characteristics of chapter 10). therefore the 68 series mpu interface differs from the 80 series mpu interface in that rd(e) is set to 1 (h) at status read and display data read in the command description and command table. the command description is given below by taking the 80 series mpu interface as an example. when selecting the serial interface, enter sequential data from d 7 . command description (1) display on/off this command specifies display on/off. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 0 1 0 1 0 1 0 1 1 1 1 display on 0 display off for display off, the segment and common drivers output the v dd level. (2) display start line set this command specifies the display start line address of the display data ram shown in fig. 4. the display area is displayed for 65 lines for the S1D15705 ***** , 33 lines for the s1d15707 ***** and 17 lines for the s1d15708 ***** from the specified line address to the line address increment direction. when this command is used to dynamically change the line address, the vertical smooth scroll and page change are enabled. for details, see the line address circuit of function description . e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 line address 01001000000 0 000001 1 000010 2
S1D15705 series technical manual rev. 3.2 epson 39 (3) page address set this command specifies the page address that corresponds to the low address when accessing the display data ram shown in fig. 4 from the mpu side. the display data ram can access desired bits when the page address and column address are specified. even when the page address is changed, the display state will not be changed. for details, see the page address circuit of function description . e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 page address 01010110000 0 0001 1 0010 2 (4) column address set this command specifies the column address of the display data ram shown in fig. 4. the column address is set (basically successively) by dividing it into high-order four bits and low-order four bits. since the column address is automatically incremented by 1 whenever the display data ram is accessed. the mpu can successively read/write the display data. the column address stops the increment at c7h. in this case, the page address is not changed successively. for details, see the column address circuit of function description . e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 high-order bit a7 a6 a5 a4 a3 a2 a1 a0 column address 00000000 0 00000001 1 00000010 2
S1D15705 series technical manual 40 epson rev. 3.2 (5) status read e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 busy adc on/off reset 0 0 0 0 busy when busy=1, indicates an internal operation being done or reset. the command cannot be accepted until busy=0 is reached. however, if the cycle time is satisfied, the command needs not be checked. adc indicates the correspondence relationship between the column address and segment driver. 0: reversal (column address 199 C n ? ? (6) display data write this command writes 8-bit data to the specified address of the display data ram. since the column address is automatically incremented by 1 after the data is written, the mpu can successively write the display data. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 write data (7) display data read this command reads the 8-bit data in the specified address of the display data ram. since the column address is automatically incremented by 1 after the data is written, the mpu can successively read the data consisting of multiple words. besides, immediately after the column address is set, dummy read is required one time. for details, see the description of the display data ram and internal register access of function description . when using the serial interface, the display cannot be read. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 read data
S1D15705 series technical manual rev. 3.2 epson 41 (8) adc select (segment driver direction select) this command can reverse the correspondence relationship between the column address of the display ram data shown in fig. 4 and the segment driver output. therefore the order of the segment driver output pin can be reversed using the command. after the display data is written and read, the column address is incremented by 1 according to the column address of fig. 4. for details, see the column address circuit of function description . e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 01010100000 cl ockwise (normal rotation) 1 counterclockwise (reversal) (9) display normal rotation/reversal this command can reversal display lighting and non-lighting without overwriting the contents of display data ram. in this case, the contents of display data ram are held. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 01010100110 lcd on potential (normal rotation) ram data high 1 lcd on potential (reversal) ram data low (10) display all lighting on/off this command can forcedly make all display set in the lighting state irrespective of the contents of display data ram. in this case, the contents of display data ram are held. this command has priority over the display normal rotation/reversal command. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 01010100100 normal display state 1 display all lighting (11) lcd bias set this command selects the bias ratio of the voltage required for liquid crystal drive. the command is valid when the v/ f circuit of the power supply circuit is operated. e r/w selected state a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 S1D15705 ***** s 1d15707 ***** / s1d15708 ***** 01010100010 1/9 bias 1/6 bias 1 1/7 bias 1/5 bias
S1D15705 series technical manual 42 epson rev. 3.2 (12) read modify write this command is used together with the end command. once this command is entered, the column address can be incremented by 1 only using the display data write command instead of being changed using the display read command. this state is held until the end command is entered. when the end command is entered, the column address returns to the address when the read modify write command is entered. this function can reduce the load of the mpu when repeatedly changing data for a specific display area such as a blinking cursor. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100000 * the commands other than display data read/write can be used even in read modify write mode. however, the column address set command cannot be used. sequence for cursor display fig. 16 page address set column address set dummy read data read data write data processing end yes no is the change terminated? read modify write
S1D15705 series technical manual rev. 3.2 epson 43 (13) end this command resets the read modify write mode and returns the column address to the mode initial address. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011101110 (14) reset this command initializes display start line, column address, page address, common output state, v 5 voltage adjusting built-in resistance ratio, electronic control, and static indicator and resets the read modify write mode and test mode. this will not have any effect on the display data ram. for details, see the reset of function description . reset operation is performed after the reset command is entered. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100010 the initialization when the power is applied is performed using the reset signal to the res pin. the reset command cannot be substituted for the signal. (15) common output state selection this command can select the scanning direction of the com output pin. for details, see the common output state selection circuit of function description . e r/w selected state a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 S1D15705 ***** s1d15707 ***** s1d15708 ***** 0 1 0 11000* * * normal rotation com0 ? ? ? n+3 n+2 n+1 n column address read modify write mode set end return
S1D15705 series technical manual 44 epson rev. 3.2 (16) power control set this command sets the function of the power supply circuit. for details, see the power supply circuit of function description . e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 selected state 010001010 boosting circuit: off 1 boosting circuit: on 0 v adjusting circuit: off 1 v adjusting circuit: on 0 v/f circuit: off 1 v/f circuit: on (v/f circuit: voltage follower circuit, v adjusting circuit: voltage adjusting circuit) (17) v 5 voltage adjusting built-in resistance ratio set this command sets the v 5 voltage adjusting built-in resistance ratio. for details, see the power supply circuit of function description . e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 rb to ra ratio 01000100000 small 001 010 (18) electronic control (2-byte command) this command controls the liquid crystal drive voltage v 5 output from the voltage adjusting circuit of the built-in liquid crystal power supply and can adjust the light and shade of liquid crystal display. since this command is a 2-byte command that is used together with the electronic control mode set command and electronic control register set command, always use both the commands consecutively. electronic control mode set entering this command validates the electronic control register set command. once the electronic control mode is set, the commands other than the electronic control register set command cannot be used. this state is reset after data is set in the register using the electronic control register set command. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01010000001
S1D15705 series technical manual rev. 3.2 epson 45 electronic control register set this command is used to set 6-bit data in the electronic volume register to allow the liquid crystal drive voltage v 5 to enter one-state voltage value among 64-state voltage values. after this command is entered and the electronic control register is set, the electronic control mode is reset. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 | v5 | 010* *000000 small 010* *000001 010* *000010 when not using the electronic control function, set (1,0,0,0,0,0). sequence of the electronic control register set fig. 18 (19) static indicator (2-byte command) this command controls the indicator display of the static drive system. the static indicator display is controlled only using this command, and this command is independent of other display control commands. the static indicator is used to connect the sync pin to one of its liquid crystal drive electrodes and the frs pin to the other. for the electrodes used for the static indicator, the pattern separated from the electrodes for dynamic drive are recommended. when this pattern is too adjacent, the deterioration of liquid crystal and electrodes may be caused. since the static indicator on command is a 2-byte command that is used together with the static indicator register set command, always use both the commands consecutively. (the static indicator off command is a 1-byte command.) electronic control mode set electronic control register set electronic control mode reset yes no is the change terminated?
S1D15705 series technical manual 46 epson rev. 3.2 static indicator on/off entering the static indicator on command validates the static indicator register set command. once the static indicator on command is entered, the commands other than the static indicator register set command cannot be used. this state is reset after the data is set in the register using the static indicator register set command. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 static indicator 01010101100 off 1on static indicator register set this command sets data in the 2-bit static indicator register and sets the blinking state of the static indicator. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 indicator display state 010******00 off 0 1 on (blinks at an interval of approximately 0.5 second.) 1 0 on (blinks at an interval of approximately one second.) 1 1 on (goes on at all times.) *: invalid bit sequence of static indicator register set fig. 19 static indicator on static indicator register set yes no is the change terminated? (static indicator mode reset)
S1D15705 series technical manual rev. 3.2 epson 47 (20) power save this command makes the static indicator enter the power save state and can greatly reduce the power consumption. the power save state consists of the sleep state and stand-by state. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 power save state 01010101000 st and-by state 1 sleep state the operating state before the display data and power save activation is held in the sleep and stand-by states, and the display data ram can also be accessed from the mpu. sleep state this command stops all the operations of lcd display systems, and can reduce the power consumption approximate to the static current when they are not accessed from the mpu. the internal state in the sleep state is as follows: (1) the oscillator circuit and the lcd power supply circuit are stopped. (2) all liquid crystal drive circuit is stopped and the segment and common drivers output the v dd level. stand-by state this command stops the operation of the duty lcd display system and operates only the static drive system for indicators. consequently the minimum current consumption required for the static drive is obtained. the internal state in the stand-by state is as follows: (1) the lcd power supply circuit is stopped. the oscillator circuit is operated. (2) the duty drive system liquid crystal drive circuit is stopped and the segment and common drivers output the v dd level. the static drive system is operated. * when using external power supplies, it is recommended that the function of the external power supply circuit should be stopped at power save activation. for example, when providing each level of the liquid crystal drive voltage using a stand-alone split resistor circuit, it is recommended that the circuit which cuts off the current applied to the split resistor circuit should be added at power save activation. the S1D15705 series has the liquid crystal display blanking control pin dof and is set to low at power save activation. the function of the external power supply circuit can be stopped using the dof output. (21) power save reset this command resets the power save state and returns the state before power save activation. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100001 (22) n-line reversal drive register set this command sets the number of reversal lines of the liquid crystal drive in the register. 2 to 16 lines can be set. for details, see the display timing generator circuit of function description . e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 line of reversal lines 01000110000 0001 2 0010 3
S1D15705 series technical manual 48 epson rev. 3.2 (23) n-line reversal drive reset this command resets the n-line reversal alternating current drive and returns to the normal 2-frame reversal alternating current drive system. the value of the n-line reversal alternating current drive register is not changed. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100100 (24) built-in oscillator circuit on this command starts the operation of the built-in cr oscillator circuit. this command is valid only for the master operation (m/s=high) and built-in oscillator circuit valid (cls=high). e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01010101011 (25) nop non-operation e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100011 (26) test ic chip test command. do not use this command. if the test command is used incorrectly, it can be reset by setting the res input to low or by using the reset command or nop. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101111* * * * *: invalid bit (note) although the S1D15705 series holds the command operating state, it may change the internal state if excessive foreign noise is entered. such action that suppresses the generation of noise and prevents the effect of noise needs to be taken on installation and systems. besides, to prevent sudden noise, it is recommended that the operating state should periodically be refreshed.
S1D15705 series technical manual rev. 3.2 epson 49 table 16 S1D15705 series commands command code command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function (1) display on/off 0 1 0 1 0 1 0 1 1 1 0 lcd display on/off 1 0: off, 1: on (2) display start line set 0 1 0 0 1 display start address sets the display start line address of the display ram. (3) page address set 0 1 0 1 0 1 1 page sets the page address of address the display ram. (4) column address set 0 1 0 0 0 0 1 high order sets the high-order four bits of high-order bit column the column address of the display address ram. column address set 0 1 0 0 0 0 0 low order sets the low-order four bits of low-order bit column the column address of the display address ram. (5) status read 0 0 1 status 0 0 0 0 reads the status information. (6) display data read 1 1 0 write data writes data on the display ram. (7) display data write 1 0 1 read data reads data from the display ram. (8) adc select 0 1 0 1 0 1 0 0 0 0 0 supports the seg output of 1 the display ram address. 0: normal rotation, 1: reversal (9) display normal 0 1 0 1 0 1 0 0 1 1 0 lcd display normal rotation/ rotation/reversal 1 reversal 0: normal rotation, 1: reversal (10) display all lighting 0 1 0 1 0 1 0 0 1 0 0 display all lighting on/off 1 0: normal display, 1: all on (11) lcd bias set 0 1 0 1 0 1 0 0 0 1 0 sets the lcd drive voltage bias ratio. 1 S1D15705 ***** 0: 1/9, 1: 1/7, s1d15707 ***** 0: 1/6, 1: 1/5 (12) read modify write 0 1 0 1 1 1 0 0 0 0 0 increments the column address. at write operation: by 1, at read: 0 (13) end 0 1 0 1 1 1 0 1 1 1 0 resets read modify write. (14) reset 0 1 0 1 1 1 0 0 0 1 0 internal resetting (15) common output state 0 1 0 1 1 0 0 0 * * * selects the scanning direction of selection the com output. 1 0: normal rotation, 1: reversal (16) power control set 0 1 0 0 0 1 0 1 operating selects the state of the built-in state power supply (17) v 5 voltage adjusting internal 0 1 0 0 0 1 0 0 resistance selects the state of the built-in resistance ratio set ratio setting resistance ratio (rb/ra). (18) electronic control 0 1 0 1 0 0 0 0 0 0 1 mode set electronic control 0 1 0 * * electronic sets the v 5 output voltage register set control value in the electronic register. (19) static indicator on/off 0 1 0 1 0 1 0 1 1 0 0 0: off, 1: on 1 static indicator 0 1 0 * ***** state sets the blinking state. register set (20) power save 0 1 0 1 0 1 0 1 0 0 0 moves to the power save state. 1 0: stand-by, 1: sleep (21) power save reset 0 1 0 1 1 1 0 0 0 0 1 resets power save. (22) n-line reversal drive 0 1 0 0 0 1 1 number of sets the number of line register set reversal line reversal drive lines. (23) n-line reversal drive reset 0 1 0 1 1 1 0 0 1 0 0 resets the line reversal drive. (24) built-in oscillator 0 1 0 1 0 1 0 1 0 1 1 starts the operation of the built-in circuit on cr oscillator circuit. (25) nop 0 1 0 1 1 1 0 0 0 1 1 non-operation command (26) test 0 1 0 1 1 1 1 * * * * do not use the ic chip test command. *: invalid bit
S1D15705 series technical manual 50 epson rev. 3.2 8. command setting instruction setup: reference (1) initial setting notes: reference items *1: if external power supplies for driving lcd are used, do not supply voltage on v out or v 5 pin during the period when res = low. instead, input voltage after releasing the reset state. 6. function description reset circuit *2: the contents of ddram are not defined even in the initial setting state after resetting. 6. function description section reset circuit *3: 7. command description item (21) power save reset *4: 7. command description item (24) built-in oscillator circuit on *5: 7. command description item (11) lcd bias set *6: 7. command description item (8) adc select *7: 7. command description item (15) common output state selection *8: 6. function description section display timing generator circuit , 7. command description item (22) n-line reversal register set *9: 6. function description section power supply circuit and 7. command description item (17) v 5 voltage adjusting built-in resistance ratio set *10: 6. function description section power supply circuit and 7. command description item (18) electronic control *11: 6. function description section power supply circuit and 7. command description item (16) power control set turn on the v dd - v ss power supply in the res pin=low *1 power supply regulated initial setting state (default) *2 end of initial setting function setting by command input (set by user) (11) lcd bias set *5 (8) adc select *6 (15) common output state selection *7 (22) n-line reversal register set *8 (when the n-line alternating current reversal drive is used) function setting by command input (set by user) (17) v 5 voltage adjusting built-in resistance ratio set *9 (18) electronic control *10 function setting by command input (set by user) (21) power save reset *3 (24) built-in oscillator circuit on *4 (the built-in cr oscillator circuit is used) function setting by command input (set by user) (16) power control set *11 reset the reset state (res pin=high)
S1D15705 series technical manual rev. 3.2 epson 51 (2) data display notes: reference items *12: 7. command description item (2) display start line set *13: 7. command description item (3) page address set *14: 7. command description item (4) column address set *15: the contents of ddram is not defined after completing initial setting. enter data in each ddram to be used for display. 7. command description item (6) display data write *16: avoid activating the display function with entering space characters as the data if possible. 7. command description item (1) display on/off (3) refresh *17 a desired mode set all commands again function setting by command (21) power save reset (22) nop write in the display data ram again notes: reference items *17: it is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of unexpected noise. input (21) power save reset and (22) nop in order to avoid going into a power save state and ic tip test state accidentally. end of data display end of initial setting function setting by command input (set by user) (2) display start line set *12 (3) page address set *13 (4) column address set *14 function setting by command input (set by user) (1) display on/off *16 function setting by command input (set by user) (6) display data write *15
S1D15705 series technical manual 52 epson rev. 3.2 100 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 v 5 voltage discharge time [ms] capacity c2 [ notes: reference items *18: this ic is a v dd v ss power system circuit controlling the lcd driving circuit for the v dd v 5 power system. shutting of power with voltage remaining in the v dd v 5 power system may cause uncontrolling voltage to be output from the seg and com pins. follow the power off sequence. *19: 7. command description item power saving *20: when external power supplies for driving lcd are used, turn all external power supplies off before entering reset state. 6. function description item reset circuit *21: the reference value for the threshold voltage of the lcd panel is 1 [v]. when the built-in power circuit is used, the discharge time, t h , or the time interval between the point when the reset state has started and the point when voltage between v dd and v 5 becomes 1 [v] depends on the v dd v ss power voltage and the capacity c2 connected between v 1 v 5 and v dd . any desired state function setting by command input (set by user) (20) power save *19 set the time interval after the point when reset state has attained and the point when v dd C v ss power is shut off ( t l ) so that electric potentials, v1 through v5, attain values lower than the threshold voltage displayed on the lcd panel. *21 reset state (res pin=low) *20 v dd C v ss power off (4) power off *17
S1D15705 series technical manual rev. 3.2 epson 53 v dd v dd v 1 v 2 v 3 v 4 v 5 res seg com power off t l t h 2.4 [v] as power (v dd C v ss ) is shut off, it becomes unable to fix output. at or under vth on lcd. use 1.0 [v] as a reference. take action so that the relationship, t l > t h , is maintained by measures such as making the trailing characteristic longer. if command control is disabled when power is off, take action so that the relationship, t l > t h , is maintained by measures such as making the trailing characteristic of power (v dd v ss ) longer. fig. 22 set up t l so that the relationship, t l > t h , is maintained. a state of t l < t h may cause faulty display. v dd v dd v 1 v 2 v 3 v 4 v 5 res seg com power off power saving 2.4 [v] as power (v dd C v ss ) is shut off, it becomes impossible to fix output. at or under vth on lcd. use 1.0 [v] as a reference. t l t h fig. 21
S1D15705 series technical manual 54 epson rev. 3.2 9. absolute maximum ratings table 17 v ss =0 v unless specified otherwise item symbol specification value unit power supply voltage v dd C 0.3 to +7.0 v power supply voltage (2) C 7.0 to +0.3 (based on v dd ) at triple boosting v ss2 C 6.0 to +0.3 at quadruple boosting C 4.5 to +0.3 power supply voltage (3) (based on v dd )v 5 , v out C 20.0 to +0.3 power supply voltage (4) (based on v dd )v 1 , v 2 , v 3 , v 4 v 5 to +0.3 input voltage v in C 0.3 to v dd +0.3 output voltage v o C 0.3 to v dd +0.3 operating temperature t opr C 40 to +85 C 55 to +100 bare chip C 55 to +125 fig. 23 (notes) 1. the values of the v ss2 , v 1 to v 5 , and v out voltages are based on v dd =0 v. 2. the v 1 , v 2 , v 3 , and v 4 voltages must always satisfy the condition of v dd v 1 v 2 v 3 v 4 v 5 . 3. the v ss2 and v out voltages must always satisfy the condition of v dd v ss v ss2 v out . 4. when lsi is used exceeding the absolute maximum ratings, the lsi may be damaged permanently. besides, it is desirable that the lsi should be used in the electrical characteristics condition for normal operation. if this condition is exceeded, the lsi may malfunction and have an adverse effect on the reliability of the lsi. v dd v dd v ss2 , v 1 to v 4 v 5 , v out v cc gnd v ss S1D15705 side system (mpu) side
S1D15705 series technical manual rev. 3.2 epson 55 10. dc characteristics table 18 unless otherwise specified, v ss =0 v, ta= 40 to +85 c specification value applicable item symbol condition min. typ. max. unit pin operating voltage (1) v dd S1D15705 * 03 ** /s1d15707 * 03 ** 2.4 3.6 v v dd *1 v dd S1D15705 * 00 ** /s1d15707 * 00 ** 3.6 5.5 v dd *1 /s1d15708 * 00 ** operating voltage (2) v ss2 (based on vdd) C 6.0 C 1.8 v ss2 operating voltage (3) v 5 S1D15705 ***** (based on v dd ) C 18.0 C 4.5 v 5 *2 v 5 s1d15707 ***** (based on v dd ) C 16.0 C 4.5 v 5 *2 v 5 s1d15708 ***** (based on v dd ) C 10.0 C 4.5 v 5 *2 v 1 , v 2 (based on vdd) 0.4 v dd v 1 , v 2 v 3 , v 4 (based on v dd )v 5 0.6 v dd *3 low level input voltage v ilc v ss 0.2 C 0.5ma 0.8 v dd *4 low level output voltage v olc i ol =0.5ma v ss 0.2 C 1.0 1.0 C 3.0 3.0 *6 liquid crystal driver r on ta=25 C 14.0v 2.0 3.5 k ? C 8.0v 3.2 5.4 comn *7 static current consumption i ssq 0.01 5 C 18.0v (based on v dd ) 0.01 15 v 5 input pin capacity c in ta=25 5.0 8.0 pf oscillating built-in f osc ta=25 specification value applicable item symbol condition min. typ. max. unit pin input voltage v ss2 at triple boosting C 6.0 C 1.8 v v ss2 (based on v dd ) v ss2 at quadruple boosting C 4.5 C 1.8 v ss2 (based on v dd ) boosting output voltage v out (based on v dd ) C 20.0 v out voltage adjusting circuit v out (based on v dd ) C 20.0 C 6.0 v out operating voltage v/f circuit operating v 5 S1D15705 ***** (based on v dd ) C 18.0 C 4.5 v 5 *9 voltage v 5 s1d15707 ***** (based on v dd ) C 16.0 C 4.5 v 5 *9 v 5 s1d15708 ***** (based on v dd ) C 10.0 C 4.5 v 5 *9 reference voltage v reg0 ta=25 C 0.05%/ C 2.04 C 2.10 C 2.16 *10 [*: see page 61.] built-in power supply circuit
S1D15705 series technical manual 56 epson rev. 3.2 dynamic current consumption value (1) during display operation and built-in power supply off current values dissipated by the whole ic when the external power supply is used table 20-1 display all white ta=25 specification value item symbol condition min. typ. max. unit remarks S1D15705 * 00 ** i dd v dd =5.0v, v 5 C v dd = C 11.0v 22 37 C v dd = C 11.0v 22 37 s1d15707 * 00 ** v dd =5.0v, v 5 C v dd = C 8.0v 8 14 s1d15707 * 03 ** v dd =3.0v, v 5 C v dd = C 8.0v 8 14 s1d15708 * 00 ** v dd =5.0v, v 5 C v dd = C 6.0v 4 7 dynamic current consumption value (2) during display operation and built-in power supply on current values dissipated by the whole ic containing the built-in power supply circuit table 21-1 display checker pattern ta=25 specification value item symbol condition min. typ. max. unit remarks S1D15705 * 00 ** i dd v dd =5.0v, normal mode 73 122 C v dd = C 11.0v high power mode 216 360 S1D15705 * 03 ** v dd =3.0v, normal mode 92 154 quadruple boosting v 5 C v dd = C 11.0v high power mode 272 454 s1d15707 * 00 ** v dd =5.0v, normal mode 40 67 triple boosting v 5 C v dd = C 8.0v high power mode 171 285 s1d15707 * 03 ** v dd =3.0v, normal mode 51 85 quadruple boosting v 5 C v dd = C 8.0v high power mode 228 380 s1d15708 * 00 ** v dd =5.0v, normal mode 28 47 double boosting v 5 C v dd = C 6.0v high power mode 137 229 [*: see page 61.] table 20-2 display checker pattern ta=25 specification value item symbol condition min. typ. max. unit remarks S1D15705 * 00 ** i dd v dd =5.0v, v 5 C v dd = C 11.0v 33 55 C v dd = C 11.0v 32 54 s1d15707 * 00 ** v dd =5.0v, v 5 C v dd = C 8.0v 14 24 s1d15707 * 03 ** v dd =3.0v, v 5 C v dd = C 8.0v 14 24 s1d15708 * 00 ** v dd =5.0v, v 5 C v dd = C 6.0v 5 9
S1D15705 series technical manual rev. 3.2 epson 57 current consumption at power save v ss =0 v and v dd = 3.0 v 10% (S1D15705 * 03 ** , s1d15707 * 03 ** ) 5.0v 10% (S1D15705 * 00 ** , s1d15707 * 00 ** , s1d15708 * 00 ** ) table 21-2 display checker pattern ta=25 specification value item symbol condition min. typ. max. unit remarks S1D15705 * 00 ** i dd v dd =5.0v, normal mode 97 162 C v dd = C 11.0v high power mode 254 424 S1D15705 * 03 ** v dd =3.0v, normal mode 130 217 quadruple boosting v 5 C v dd = C 11.0v high power mode 308 514 s1d15707 * 00 ** v dd =5.0v, normal mode 54 90 triple boosting v 5 C v dd = C 8.0v high power mode 185 309 s1d15707 * 03 ** v dd =3.0v, normal mode 71 119 quadruple boosting v 5 C v dd = C 8.0v high power mode 248 414 s1d15708 * 00 ** v dd =3.0v, normal mode 35 59 double boosting v 5 C v dd = C 6.0v high power mode 144 240 table 22 ta=25 c specification value item symbol condition min. typ. max. unit remarks sleep state i dds1 ta=25 0.01 5 48 [*: see page 61.]
S1D15705 series technical manual 58 epson rev. 3.2 [reference data 1] dynamic current consumption (1) external power supply used and lcd being displayed [reference data 2] dynamic current consumption (2) built-in power supply used and lcd being displayed condition: built-in power supply off external power supply used S1D15705: v 5 v dd = 11.0 v s1d15707: v 5 v dd = 8.0 v s1d15708: v 5 v dd = 6.0 v display pattern: all white/checker ta = 25 c remarks: *11 condition: built-in power supply on normal mode quadruple boosting S1D15705: v 5 v dd = 11.0 v triple boosting s1d15707: v 5 v dd = 8.0 v double boosting s1d15708: v 5 v dd = 6.0 v display pattern: all white/checker ta = 25 c remarks: *12 [*: see page 61.] 40 30 20 10 0 024 3.6 6 8 v dd [v] i dd (1) (i ss + i 5 ) [
S1D15705 series technical manual rev. 3.2 epson 59 [reference data 3] dynamic current consumption (3) during access indicates the current consumption when the checker pattern is always written at f cyc . only i dd (1) when not accessed condition: built-in power supply off and external power supply used S1D15705: v 5 v dd = 11.0 v s1d15707: v 5 v dd = 11.0 v S1D15705 * 03 ** /s1d15707 * 03 ** : v dd v ss = 3.0 v S1D15705 * 00 ** /s1d15707 * 00 ** /s1d15708 * 00 ** : v dd v ss = 5.0 v ta = 25 c [*: see page 61.] 10 1 0.1 0.01 0.001 0.01 0.1 1 10 f cyc [mhz] i dd (3) [ma] S1D15705 * 00 ** S1D15705 * 03 ** s1d15707 * 00 ** s1d15707 * 03 ** s1d15708 * 00 ** fig. 26
S1D15705 series technical manual 60 epson rev. 3.2 v ss and v 5 system operating voltage ranges remarks: *2 [*: see page 61.] [reference data 4] C 20 C 15 C 10 C 5 0 02468 2.4 3.6 5.5 C 9.6 C 18 C 4.5 S1D15705 * 03 ** S1D15705 * 00 ** operation area v dd [v] v 5 - v dd [v] C 20 C 15 C 10 C 5 0 02468 3.6 5.5 C 4.5 s1d15708 * 00 ** operation area v dd [v] v 5 - v dd [v] C 20 C 15 C 10 C 5 0 02468 2.4 3.6 5.5 C 9.6 C 16 C 4.5 s1d15707 * 03 ** s1d15707 * 00 ** operation area v dd [v] v 5 - v dd [v] fig. 27
S1D15705 series technical manual rev. 3.2 epson 61 table 23 f fr item f cl normal duty drive n-line reverse drive S1D15705 ***** when built-in oscillator f osc f osc f osc circuit used 4 4.65 4.n when built-in oscillator external input (f cl )f cl f cl circuit not used 65 n s1d15707 ***** when built-in oscillator f osc f osc f osc circuit used 8 8.33 8.n when built-in oscillator external input (f cl )f cl f cl circuit not used 33 n s1d15708 ***** when built-in oscillator f osc f osc f osc circuit used 16 16.17 16.n when built-in oscillator external input (f cl )f cl f cl circuit not used 17 n relationships between the oscillating frequency f osc , display clock frequency f cl , and liquid crystal frame frequency f fr [reference items marked by *] *1 the wide operating voltage range is not warranted. however, when there is a sudden voltage change during mpu access, it cannot be warranted. *2 for the v dd and v 5 operating voltage ranges, see fig. 27. these ranges are applied when using the external power supply. *3 a0, d0 to d5, d6 (scl), d7 (si), rd (e), wr (r/w), cs1, cs2, cls, cl, fr, m/s, c86, p/s, dof, res, irs and hpm pins *4 d0 to d7, fr, frs, dof and cl pins *5 a0, rd (e), wr (r/w), cs1, cs2, cls, m/s, c86, p/s, res, irs and hpm pins *6 applied when d0 to d5, d6 (scl), d7 (si), cl, fr, and dof pins are in the high impedance state *7 resistance value when the 0.1 v voltage is applied between the output pin segn or comn and power supply pins (v 1 , v 2 , v 3 , and v 4 ). specified within the range of operating voltage (3) r on = 0.1 v/ ? i ( ? i indicates the current applied when 0.1 v is applied between the power on.) *8 for the relationship between the oscillating frequency and frame frequency, see table 23. the specification value of the external input item is a recommended value. *9 the v 5 voltage adjusting circuit is adjusted within the voltage follower operating voltage range. *10 built-in reference voltage source of the v 5 voltage adjusting circuit. *11 and *12 indicate the current dissipated by a single ic at built-in oscillator circuit used, 1/9 bias (S1D15705 ***** ), 1/6 bias (s1d15707 ***** /s1d15708 ***** ), and display on. does not include the current due to the lcd panel capacity and wireing capacity. applicable only when there is no access from the mpu. *12 when the v 5 voltage adjusting built-in resistor is used (f fr shows the alternating current cycle (frame cycle) of liquid crystal. the signal of fr terminal becomes twice as a frame cycle.)
S1D15705 series technical manual 62 epson rev. 3.2 timing characteristics system bus read/write characteristics 1 (80 series mpu) a0 cs1 (cs2="1") wr, rd d0 to d7 (write) d0 to d7 (read) t acc8 t oh8 t ds8 t cyc8 t ah8 t aw8 t cclr , t cclw t cchr , t cchw t dh8 t r t f cs1 (cs2="1") wr, rd *1 *2 [S1D15705 * 00 ** , s1d15707 * 00 ** , s1d15708 * 00 ** : v dd =4.5v to 5.5v, ta= C 40 to +85 specification value item signal symbol condition min. max. unit address hold time a0 t ah8 0 ns address setup time t aw8 0 system cycle time t cyc8 250 control low pulse width (write) wr t cclw 30 control low pulse width (read) rd t cclr 70 control high pulse width ( write ) wr t cchw 30 control high pulse width (read) rd t cchr 30 data setup time d0 to d7 t ds8 30 data hold time t dh8 10 rd access time t acc8 c l =100pf 70 output disable time t oh8 550
S1D15705 series technical manual rev. 3.2 epson 63 [S1D15705 * 00 ** , s1d15707 * 00 ** , s1d15708 * 00 ** : v dd =3.6v to 4.5v, ta= C 40 to +85 specification value item signal symbol condition min. max. unit address hold time a0 t ah8 0 ns address setup time t aw8 0 system cycle time t cyc8 300 control low pulse width ( write ) wr t cclw 60 control low pulse width ( read ) rd t cclr 120 control high pulse width (write) wr t cchw 60 control high pulse width (read) rd t cchr 60 data setup time d0 to d7 t ds8 40 data hold time t dh8 15 rd access time t acc8 c l =100pf 280 output disable time t oh8 10 100 [S1D15705 * 03 ** , s1d15707 * 03 ** : v dd =2.4v to3.6v, ta= C 40 to +85 specification value item signal symbol condition min. max. unit address hold time a0 t ah8 0 ns address setup time t aw8 0 system cycle time t cyc8 800 control low pulse width ( write ) wr t cclw 120 control low pulse width ( read ) rd t cclr 240 control high pulse width (write) wr t cchw 120 control high pulse width (read) rd t cchr 120 data setup time d0 to d7 t ds8 80 data hold time t dh8 30 rd access time t acc8 c l =100pf 280 output disable time t oh8 10 200 *1 this is in the case of making the access by wr and rd, setting the cs1=low. *2 this is in the case of making the access by cs1, setting the wr, rd=low. *3 the rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. when using the system cycle time at high speed, they are specified for (t r +t f ) (t cyc8 t cclw t cchw ) or (t r +t f ) (t cyc8 t cclr t cchr ). *4 all timings are specified based on the 20 and 80% of v dd . *5 t cclw and t cclr are specified for the overlap period when cs1 is at low (cs2= high) level and wr, rd are at the low level.
S1D15705 series technical manual 64 epson rev. 3.2 system bus read/write characteristics 2 (68 series mpu) a0 r/w cs1 (cs2="1") e d0 to d7 (write) d0 to d7 (read) t acc6 t oh6 t ds6 t cyc6 t ah6 t aw6 t ewhr , t ewhw t ewlr , t ewlw t dh6 t f t r cs1 (cs2="1") e *1 *2 [S1D15705 * 00 ** , s1d15707 * 00 ** , s1d15708 * 00 ** : v dd =4.5v to 5.5v, ta= C 40 to +85 specification value item signal symbol condition min. max. unit address hold time a0 t ah6 0 ns address setup time t aw6 0 system cycle time t cyc6 250 data setup time d0 to d7 t ds6 30 data hold time t dh6 10 access time t acc6 c l =100pf 70 output disable time t oh6 550 enable high pulse width read e t ewhr 70 write t ewhw 30 enable low pulse width read e t ewlr 30 write t ewlw 30
S1D15705 series technical manual rev. 3.2 epson 65 [S1D15705 * 00 ** , s1d15707 * 00 ** , s1d15708 * 00 ** : v dd =3.6v to 4.5v, ta= C 40 to +85 specification value item signal symbol condition min. max. unit address hold time a0 t ah6 0 ns address setup time t aw6 0 system cycle time t cyc6 300 data setup time d0 to d7 t ds6 40 data hold time t dh6 15 access time t acc6 c l =100pf 140 output disable time t oh6 10 100 enable high pulse width read e t ewhr 120 write t ewhw 60 enable low pulse width read e t ewlr 60 write t ewlw 60 [S1D15705 * 03 ** , s1d15707 * 03 ** : v dd =2.4v to 3.6v, ta= C 40 to +85 specification value item signal symbol condition min. max. unit address hold time a0 t ah6 0 ns address setup time t aw6 0 system cycle time t cyc6 800 data setup time d0 to d7 t ds6 80 data hold time t dh6 30 access time t acc6 c l =100pf 280 output disable time t oh6 10 200 enable high pulse width read e t ewhr 240 write t ewhw 120 enable low pulse width read e t ewlr 120 write t ewlw 120 *1 this is in the case of making the access by e, setting the cs1=low. *2 this is in the case of making the access by cs1, setting the e=high. *3 the rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. when using the system cycle time at high speed, they are specified for (t r +t f ) (t cyc6 t ewlw t ewhw ) or (t r +t f ) (t cyc6 t ewlr t ewhr ). *4 all timings are specified based on the 20 and 80% of v dd . *5 t ewlw and t ewlr are specified for the overlap period when cs1 is at low (cs2= high) level and e is at the high level.
S1D15705 series technical manual 66 epson rev. 3.2 serial interface [S1D15705 * 00 ** , s1d15707 * 00 ** , s1d15708 * 00 ** : v dd =4.5v to 5.5v, ta= C 40 to +85 specification value item signal symbol condition min. max. unit serial clock cycle scl t scyc 200 ns scl high pulse width t shw 75 scl low pulse width t slw 75 address setup time a0 t sas 50 address hold time t sah 100 data setup time si t sds 50 data hold time t sdh 50 cs-scl time cs t css 100 t csh 100 t css t csh t sah t shw t sdh t sds t slw t f t r t scyc t sas cs1 (cs2="1") a0 scl si
S1D15705 series technical manual rev. 3.2 epson 67 [S1D15705 * 00 ** , s1d15707 * 00 ** , s1d15708 * 00 ** : v dd =3.6v to 4.5v, ta= C 40 to +85 specification value item signal symbol condition min. max. unit serial clock cycle scl t scyc 250 ns scl high pulse width t shw 100 scl low pulse width t slw 100 address setup time a0 t sas 150 address hold time t sah 150 data setup time si t sds 100 data hold time t sdh 100 cs-scl time cs t css 150 t csh 150 [S1D15705 * 03 ** , s1d15707 * 03 ** : v dd =2.4v to 3.6v, ta= C 40 to +85 specification value item signal symbol condition min. max. unit serial clock cycle scl t scyc 400 ns scl high pulse width t shw 150 scl low pulse width t slw 150 address setup time a0 t sas 250 address hold time t sah 250 data setup time si t sds 150 data hold time t sdh 150 cs-scl time cs t css 250 t csh 250 *1 the rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. *2 all timings are specified based on the 20 and 80% of v dd .
S1D15705 series technical manual 68 epson rev. 3.2 display control output timing t dfr t dsnc cl (out) fr sync [S1D15705 * 00 ** , s1d15707 * 00 ** , s1d15708 * 00 ** : v dd =4.5v to 5.5v, ta= C 40 to +85 specification value item signal symbol condition min. typ. max. unit fr delay time fr t dfr c l =50pf 10 40 ns sync delay time sync t dsnc c l =50pf 10 40 ns [S1D15705 * 00 ** , s1d15707 * 00 ** , s1d15708 * 00 ** : v dd =3.6v to 4.5v, ta= C 40 to +85 specification value item signal symbol condition min. typ. max. unit fr delay time fr t dfr c l =50pf 20 80 ns sync delay time sync t dsnc c l =50pf 20 80 ns [S1D15705 * 03 ** , s1d15707 * 03 ** : v dd =2.4v to 3.6v, ta= C 40 to +85 specification value item signal symbol condition min. typ. max. unit fr delay time fr t dfr c l =50pf 50 200 ns sync delay time sync t dsnc c l =50pf 50 200 ns *1 valid only when the master mode is selected. *2 all timings are specified based on the 20 and 80% of v dd . *3 pay attention not to cause delays of the timing signals cl, fr and sync to the salve side by wiring resistance, etc., while master/slave operations are in progress. if these delays occur, indication failures such as flickering may occur.
S1D15705 series technical manual rev. 3.2 epson 69 reset input timing [S1D15705 * 00 ** , s1d15707 * 00 ** , s1d15708 * 00 ** : v dd =4.5v to 5.5v, ta= C 40 to +85 specification value item signal symbol condition min. typ. max. unit reset time t r 0.5 [S1D15705 * 00 ** , s1d15707 * 00 ** , s1d15708 * 00 ** : v dd =3.6v to 4.5v, ta= C 40 to +85 specification value item signal symbol condition min. typ. max. unit reset time t r 1 [S1D15705 * 03 ** , s1d15707 * 03 ** : v dd =2.4v to 3.6v, ta= C 40 to +85 specification value item signal symbol condition min. typ. max. unit reset time t r 1.5 *1 all timings are specified based on the 20 and 80% of v dd . t rw t r completion of reset resetting res internal state
S1D15705 series technical manual 70 epson rev. 3.2 11. microprocessor (mpu) interface: reference the S1D15705 series can directly be connected to the 80 system mpu and 68 series mup. it can also be operated with a fewer signal lines by using the serial interface. the S1D15705 series is used for the multiple chip configuration to expand the display area. in this case, it can select the ics that are accessed individually using the chip select signal. after the initialization using the res pin, the respective input pins of the S1D15705 series need to be controlled normally. 80 series mpu v dd v cc gnd decoder reset mpu a0 d0 to d7 rd wr res cs1 cs2 a0 d0 to d7 rd wr res a1 to a7 iorq v dd c86 p/s v ss v ss S1D15705 68 series mpu v dd v cc gnd decoder reset mpu a0 d0 to d7 e r/w res cs1 cs2 a0 d0 to d7 e r/w res a1 to a15 vma v dd c86 p/s v ss v ss S1D15705 serial interface v dd v cc gnd decoder reset mpu a0 si scl res cs1 cs2 a0 port 1 port 2 res a1 to a7 v dd or v ss c86 p/s v ss v ss S1D15705
S1D15705 series technical manual rev. 3.2 epson 71 12. connection between lcd drivers: reference the S1D15705 series is used for the multiple chip configuration to easily expand the liquid crystal display area. use the same device (S1D15705 ***** /S1D15705 ***** , s1d15707 ***** /s1d15707 ***** or s1d15708 ***** / s1d15708 ***** ) for the master/slave. S1D15705 (master) ? ? ? ? ? S1D15705 (slave) v ss v dd m/s output input S1D15705 master m/s fr sync cl dof fr sync cl dof S1D15705 slave
S1D15705 series technical manual 72 epson rev. 3.2 13. lcd panel wiring: reference the S1D15705 series is used for the multiple chip configuration to easily expand the liquid crystal display area. use the same device (S1D15705 ***** /S1D15705 ***** , s1d15707 ***** /s1d15707 ***** or s1d15708 ***** / s1d15708 ***** ) for the multiple chip configuration. 1-chip configuration 168 x 65 dots com seg com S1D15705 master 2-chip configuration 336 x 65 dots com com seg seg S1D15705 series master S1D15705 series slave
S1D15705 series technical manual rev. 3.2 epson 73 14. tcp pin layout fr cl dof sync cs1 cs2 res a0 wr,r/w rd, e d0 d1 d2 d3 d4 d5 d6, scl d7, si v dd v ss v ss2 v out cap3- cap1+ cap1- cap2- cap2+ vrs v dd v 1 v 2 v 3 v 4 v 5 vr v dd m/s cls c86 p/s hpm irs frs sync com s com 63 com 33 com 32 seg 167 seg 166 seg 1 seg 0 com s com 0 com 30 com 31 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chip top view reference note) this tcp pin layout does not specify the tcp dimensions.
S1D15705 series technical manual 74 epson rev. 3.2 15. tcp dimensions (mold,marking area) (mold,marking area)part b part a output terminal pattern shape part b detail for test pad specifications ? base: u-rex s 75 ? copper foil : electrolytic copper foil, 25 ? sn plating ? product pitch : 41p (19.0mm) ? solder resist positional tolerance:
S1D15705 series technical manual rev. 3.2 epson 75 16. temperature sensor circuit S1D15705 * 10 ** incorporates a temperatujre sensor circuit with a 11.4mv/ c (typ.) temperature gradient carrying analog voltage output pins. the S1D15705 * 10 ** makes it possible to provide lcd indications with optimum contrast throughout a wide temperature range without need for use of supplementary parts by inputting electronic volume control registration value equivalent signals corresponding to the outputs of the temperature sensor through the mpu to control the lcd drive voltage v 5 . for lcd drive voltage controls of higher precision, we recommend you to constitute a system which can absorb deviations of the output voltage by, such as, feeding back sampled output voltages under a certain temperature environment to the mpu to let it memorize as the reference voltages. regarding the specifications of other items than the temperature sensor circuit, such as of the absolute maximum ratings, dc characteristics, ac characteristics, etc., refer to the specifications for S1D15705 * 00 ** . pin definitions temperature sensor circuit related pins are allocated to test1, 2, 3 and 4 and the pin names are test1, svs, v sen , sen and sensel in the given sequence. the temperature sensor should be used under the pin statuses indicated in the table below. when the temperature sensor is not being used, fix respective pins to high. electric characteristics pin names i/o pin definitions number of pins svs power this is the power supply pin for the temperature sensor. apply 1 supply prescribed operating voltage between the v dd . v sen o this is the analog voltage output pin for the temperature sensor. 1 monitor the output voltage between the v dd . sen o consider to keep this pin open in order not to apply the load 1 capacitance of wires, etc. sensel i fix this pin to high. 1 items codes conditions specifications units applicable min. typ. max. pins operating voltage svs (on the basis of v dd ) C 5.5 C 5.0 C 4.5 v svs output voltage v sen (on the basis of v dd ) C 4.35 C 3.62 C 2.89 v v sen ta = 40 C 3.48 C 2.88 C 2.28 ta = 25 C 2.92 C 2.20 C 1.47 ta = 85 * 1 9.4 11.4 13.4 mv/ ? * 2 C 1.5 1.5 % v sen output voltage setup time t sen * 3 100 ms v sen operating current i sen ta = 25 40 150
S1D15705 series technical manual 76 epson rev. 3.2 [* notes] *1: represents the gradient of the approximate line of the typ. output voltages. *2: represents the maximum deviation between the output voltage curve and the approximate line. assuming that the difference of output voltages at 40 c and at 80 c as ? v sen , assuming that the difference between the approximate line and the output voltage values as ? diff and assuming that the maximum value thereof as ? diff (max), the output voltages linearity ? v l can be calculated by use of the following equation. ? diff (max) ? v l = 100 ? v sen C 50 ? ? C 40 C v sen (85 ? ? C 25 0 25 temperature ta [ ? ? *3: represents the queuing time after the supply voltage svs is applied to the svs pin until the output voltage is stabilized and monitoring thereof becomes feasible. be sure to sample the output voltage after the prescribed queuing time has elapsed. output voltage characteristics C 25 C 50 0 C 1 C 2 C 3 C 4 C 5 025 temperature ta [
S1D15705 series technical manual rev. 3.2 epson 77 output pin load maintain the load capacity c l for the v sen output pin v sen at 100pf or less and keep the load resistance r l for the v sen output pin v sen at 1m ? or more. in order to obtain accurate output voltage values, be careful not to insert a current flowing channel between the v ss . v dd v dd v sen c l r l v sen S1D15705 series
S1D15705 series technical manual 78 epson rev. 3.2 17. cautions cautions must be exercised on the following points when using this development specification: 1. this development specification is subject to change for engineering improvement. 2. this development specification does not guarantee execution of the industrial proprietary rights or other rights, or grant a license. examples of applications described in this development specification are intended for your understanding of the product. we are not responsible for any circuit problem or the like arising from the use of them. 3. reproduction or copy of any part or whole of this development specification without permission of our company, or use thereof for other business purposes is strictly prohibited. for the use of the semi-conductor,cautions must be exercised on the following points: [cautions against light] the semiconductor will be subject to changes in characteristics when light is applied. if this ic is exposed to light, operation error may occur. to protect the ic against light, the following points should be noted regarding the substrate or product where this ic is mounted: (1) designing and mounting must be provided to get a structure which ensures a sufficient resistance of the ic to light in practical use. (2) in the inspection process, environmental configuration must be provided to ensure a sufficient resistance of the ic to light. (3) means must be taken to ensure resistance to light on all the surfaces, backs and sides of the ic
international sales operations america epson electronics america, inc. headquarters 150 river oaks parkway san jose, ca 95134, u.s.a. phone: +1-800-228-3964 fax: +1-408-922-0238 sales offices west 1960 e.grand avenue flr 2 el segundo, ca 90245, u.s.a. phone: +1-800-249-7730 fax: +1-310-955-5400 central 101 virginia street, suite 290 crystal lake, il 60014, u.s.a. phone: +1-800-853-3588 fax: +1-815-455-7633 northeast 301 edgewater place, suite 210 wakefield, ma 01880, u.s.a. phone: +1-800-922-7667 fax: +1-781-246-5443 southeast 3010 royal blvd. south, suite 170 alpharetta, ga 30005, u.s.a. phone: +1-877-332-0020 fax: +1-770-777-2637 europe epson europe electronics gmbh headquarters riesstrasse 15 80992 munich, germany phone: +49-89-14005-0 fax: +49-89-14005-110 dsseldorf branch office altstadtstrasse 176 51379 leverkusen, germany phone: +49-2171-5045-0 fax: +49-2171-5045-10 french branch office 1 avenue de l ? atlantique, lp 915 les conquerants z.a. de courtaboeuf 2, f-91976 les ulis cedex, france phone: +33-1-64862350 fax: +33-1-64862355 barcelona branch office barcelona design center edificio testa, c/alcalde barnils 64-68, modulo c 2a planta e-08190 sant cugat del vall s, spain phone: +34-93-544-2490 fax: +34-93-544-2491 uk & ireland branch office 8 the square, stockley park, uxbridge middx ub11 1fw, united kingdom phone: +44-1295-750-216/+44-1342-824451 fax: +44-89-14005 446/447 scotland design center integration house, the alba campus livingston west lothian, eh54 7eg, scotland phone: +44-1506-605040 fax: +44-1506-605041 asia epson (china) co., ltd. 23f, beijing silver tower 2# north rd dongsanhuan chaoyang district, beijing, china phone: +86-10-6410-6655 fax: +86-10-6410-7320 shanghai branch 7f, high-tech bldg., 900, yishan road, shanghai 200233, china phone: +86-21-5423-5522 fax: +86-21-5423-5512 epson hong kong ltd. 20/f., harbour centre, 25 harbour road wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx epson electronic technology development (shenzhen) ltd. 12/f, dawning mansion, keji south 12th road, hi- tech park, shenzhen phone: +86-755-2699-3828 fax: +86-755-2699-3838 epson taiwan technology & trading ltd. 14f, no. 7, song ren road, taipei 110 phone: +886-2-8786-6688 fax: +886-2-8786-6677 hsinchu office no. 99, jiangong road, hsinchu city 300 phone: +886-3-573-9900 fax: +886-3-573-9169 epson singapore pte., ltd. 1 harbourfront place, #03-02 harbourfront tower one, singapore 098633 phone: +65-6586-5500 fax: +65-6271-3182 seiko epson corporation korea office 50f, kli 63 bldg., 60 yoido-dong youngdeungpo-ku, seoul, 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 gumi office 2f, grand b/d, 457-4 songjeong-dong, gumi-city, korea phone: +82-54-454-6027 fax: +82-54-454-6093 seiko epson corporation semiconductor operations division ic sales dept. ic marketing group 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 document code: 404948101 first issue february, 2004 printed october 2005 in japan

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